EP0725402B1
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Toshiba Corp
•
Filing: 1996-01-03
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Granted: 2002-09-25
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Expires: 2016-01-03
Abstract
No abstract record available.
Inventors
- 👤 Daisaburo Takashima
- 👤 Yukihito Oowaki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 08:35
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4094; G11C11/4074; G11C11/4076; G11C11/408; G11C11/4085
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
272 words
A semiconductor memory device comprising: a plurality of word lines (WL); a plurality of bit lines (BL) intersecting the word lines; and memory cells (M) selectively arranged at intersections of the word lines (WL)
and the bit lines (BL), and each consisting of a transistor and a capacitor (C), the
transistor having a gate thereof connected to a corresponding one of the word lines
(WL), a drain thereof connected to a corresponding one of the bit lines (BL), and a
source thereof connected to an end of the capacitor and serving as a memory node, the
capacitor (C) having another end thereof connected to a plate electrode, wherein, in an active mode, assumed when a power supply is in an on state, a transistor of
a memory cell (M) which is connected to a selected one of the word lines (WL) is turned
on, and those transistors of the other memory cells (M) which are connected to non-selected
word lines (WL) are in an off state; and in a standby mode assumed when the power supply is in the on state, the
transistors of all the memory cells (M) are in an off state, when the power supply is in an off state, the transistors of all the memory cells
(M) are in an off state, and when the power supply is turned on and off, the transistors of all the memory
cells are in an off state, characterized in that the device further comprises setting means (Q14, Q15) to set the voltage of the word
line (WL) to ground level at the time of turn-on or turn-off of the power supply.
Claim 2
Dependent Claim
53 words
The semiconductor memory device according to claim 1, characterized in that in
the off state of the power supply, a node of the word line (WL) is connected to a ground
potential by means of depletion type pMOS or nMOS transistors, such that the word line
(WL) is set at the ground potential.
Claim 3
Dependent Claim
273 words
A semiconductor memory device comprising: a plurality of word lines (WL); a plurality of bit lines (BL) intersecting the word lines; and memory cells (M) selectively arranged at intersections of the word lines (WL)
and the bit lines (BL), and each consisting of a transistor and a capacitor (C), the
transistor having a gate thereof connected to a corresponding one of the word lines
(WL), a drain thereof connected to a corresponding one of the bit lines (BL), and a
source thereof connected to an end of the capacitor and serving as a memory node, the
capacitor (C) having another end thereof connected to a plate electrode, wherein, in an active mode, assumed when a power supply is in an on state, a transistor of
a memory cell (M) which is connected to a selected one of the word lines (WL) is turned
on, and those transistors of the other memory cells (M) which are connected to non-selected
word lines (WL) are in an off state; and in a standby mode assumed when the power supply is in the on state, the
transistors of all the memory cells (M) are in an off state, when the power supply is in an off state, the transistors of all the memory cells
(M) are in an off state, and when the power supply is turned on and off, the transistors of all the memory
cells are in an off state, characterized in that the device further comprises setting means (Q0 to Q4) to set the voltage
of the bit line (BL) to ground level at the time of turn-on or turn-off of the power supply.
Claim 4
Dependent Claim
53 words
The semiconductor memory device according to claim 3, characterized in that in
the off state of the power supply, a node of the bit line (BL) is connected to a ground
potential by means of depletion type pMOS or nMOS transistors, such that the bit line
(BL) is set at the ground potential.
Claim 5
Dependent Claim
30 words
The semiconductor memory device according to claim 1 or 3, characterized in
that each of the transistors is a pMOS transistor or an nMOS transistor formed on an
insulating layer.
Claim 6
Dependent Claim
46 words
The semiconductor memory device according to claim 1 or 3, characterized in
that an Si layer which constitutes at least part of a channel portion of each transistor is
thinner than the thickness of an Si layer which constitutes the source or drain of the
transistor.
Claim 7
Dependent Claim
108 words
A semiconductor memory device according to claims 1 or 3, characterized by means for receiving, from the outside of the memory device, a predetermined
signal or a predetermined command before turn-on of a power supply, or for detecting
the turn-on of the power supply, and means for receiving, from the outside of the
memory device, a predetermined signal or a predetermined command before turn-off of a
power supply, or for detecting the turn-off of the power supply, so that data stored in the
memory cells before the turn-off of the power supply can be held even when the power
supply is again turned on after the turn-off thereof.
References Cited (Backward Citations)
No citation records indexed.
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