§
Luxuse
Patent Intelligence
Sign In
Patent US6147402A successfully refreshed from Google Patents.
← Back to Patent Explorer
US6147402A Expired / Lapsed US ⏱️ 0.0 years remaining

Refractory metal capped low resistivity metal conductor lines and vias

Assignee: GlobalFoundries Inc
•
Filing: 1998-07-10
•
Granted: 2000-11-14
•
Expires: 2018-07-10
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH4 to WF6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1 mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1 mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

Inventors

  • 👤 Rajiv V. Joshi
  • 👤 Jerome J. Cuomo
  • 👤 Hormazdyar M. Dalal
  • 👤 Louis L. Hsu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 02:14
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/033; H10P; H10P14/00; H10P14/40; H10P14/42; H10P14/43; H10P14/44; H10W20/036; H10W20/037; H10W20/038; H10W20/039; H10W20/056; H10W20/062; H10W20/40; H10W20/41; H10W20/425; H10W20/44; H10W20/4403; H10W20/4421; H10W20/4424; H10W70/00; H10W70/60; H10W70/62; H10W70/66; Y; Y10; Y10S; Y10S148/00; Y10S148/015; Y10S257/00; Y10S257/915; Y10S438/00; Y10S438/959

Claims Analysis

Total Claims: 31
Claim 1
Independent Claim 64 words
A semiconductor device comprising: a dielectric layer; at least one high aspect ratio submicron hole or line in the dielectric layer; a liner in the at least one hole or line; a conductive metal or alloy within the liner, the conductive metal or alloy having a surface; and a metal-containing layer in contact with at least part of the conductive metal or alloy surface.
Claim 2
Dependent Claim 64 words
A semiconductor device comprising: a dielectric layer; at least one high aspect ratio submicron hole or line in the dielectric layer; a liner in the at least one hole or line; a conductive metal or alloy within the liner, the conductive metal or alloy having a surface; and a metal-containing layer in contact with at least part of the conductive metal or alloy surface.
Claim 3
Dependent Claim 19 words
The semiconductor device of claim 1 wherein the liner is a refractory metal or an alloy or compound thereof.
Claim 4
Dependent Claim 14 words
The semiconductor device of claim 1 wherein the conductive metal or alloy includes copper.
Claim 5
Dependent Claim 32 words
The semiconductor device of claim 1 wherein the conductive metal or alloy is the alloy Al x Cu y where x+y=1 and x and y are less than or equal to 1.
Claim 6
Dependent Claim 20 words
The semiconductor device of claim 1 wherein the metal-containing layer is a refractory metal or an alloy or compound thereof.
Claim 7
Dependent Claim 18 words
The semiconductor device of claim 1 wherein the liner and metal-containing layer are made of the same material.
Claim 8
Dependent Claim 30 words
The semiconductor device of claim 1 wherein the dielectric layer has a surface and the liner has a sidewall, wherein the sidewall terminates substantially even with the dielectric layer surface.
Claim 9
Dependent Claim 13 words
The semiconductor device of claim 1 wherein the liner is a bilayer liner.
Claim 10
Dependent Claim 30 words
The semiconductor device of claim 1 wherein the dielectric layer has a surface therein and wherein the conductive metal or alloy surface is substantially even with the dielectric layer surface.
Claim 11
Dependent Claim 22 words
The semiconductor device of claim 1 wherein the metal-containing layer is in contact with all of the conductive metal or alloy surface.
Claim 12
Dependent Claim 23 words
The semiconductor device of claim 1 wherein the dielectric layer has a surface therein and the metal-containing layer is on the dielectric surface.
Claim 13
Dependent Claim 31 words
The semiconductor device of claim 1 wherein the liner is a refractory metal or an alloy or compound thereof and the refractory metal or an alloy or compound thereof includes tantalum.
Claim 14
Dependent Claim 32 words
The semiconductor device of claim 1 wherein the metal-containing layer is a refractory metal or an alloy or compound thereof and the refractory metal or an alloy or compound thereof includes tantalum.
Claim 15
Dependent Claim 48 words
The semiconductor device of claim 1 wherein the liner is a first liner and further comprising a second dielectric layer having a second submicron hole or line therein and a second liner in the submicron hole or line wherein the metal-containing layer forms part of the second liner.
Claim 16
Dependent Claim 12 words
The semiconductor device of claim 1 wherein the liner is substantially conformal.
Claim 17
Dependent Claim 21 words
The semiconductor device of claim 7 wherein the conductive metal or alloy surface is substantially even with the dielectric layer surface.
Claim 18
Dependent Claim 22 words
The semiconductor device of claim 16 wherein the metal-containing layer is in contact with all of the conductive metal or alloy surface.
Claim 19
Dependent Claim 15 words
The semiconductor device of claim 16 wherein the metal-containing layer is on the dielectric surface.
Claim 20
Dependent Claim 23 words
The semiconductor device of claim 8 wherein at least one layer of the liner comprises a refractory metal or an alloy compound thereof.
Claim 21
Dependent Claim 36 words
The semiconductor device of claim 18 wherein the surface area of the conductive metal or alloy surface is less than the surface area of the metal-containing layer in contact with the conductive metal or alloy surface.
Claim 22
Dependent Claim 16 words
The submicron device of claim 13 wherein the dielectric layer comprises a plurality of insulating layers.
Claim 23
Dependent Claim 40 words
The semiconductor device of claim 14 wherein the second hole or line is in a surface of the second dielectric layer and the first liner has a sidewall, wherein the sidewall terminates substantially even with the second dielectric layer surface.
Claim 24
Dependent Claim 37 words
The semiconductor device of claim 14 wherein the second hole of line is in a surface of the second dielectric layer and the conductive metal or alloy surface is substantially even with the second dielectric layer surface.
Claim 25
Dependent Claim 22 words
The semiconductor device of claim 22 wherein the conductive metal or alloy surface is substantially even with the second dielectric layer surface.
Claim 26
Dependent Claim 135 words
A semiconductor device comprising: a dielectric layer; at least one high aspect ratio submicron hole or line in the dielectric layer, the at least one hole of line having at least first and second sections, wherein at least one of the width, length or height of the first section is different than the width, length or height of the second section; a first liner in the first section of the at least one hole or line; a first conductive metal of alloy within the first liner, the first conductive metal having a surface; a metal-containing layer in contact with at least part of the conductive metal or alloy surface; and a second liner in the second section of the at least one hole or line, wherein the metal-containing layer forms part of the second liner.
Claim 27
Dependent Claim 135 words
A semiconductor device comprising: a dielectric layer; at least one high aspect ratio submicron hole or line in the dielectric layer, the at least one hole of line having at least first and second sections, wherein at least one of the width, length or height of the first section is different than the width, length or height of the second section; a first liner in the first section of the at least one hole or line; a first conductive metal of alloy within the first liner, the first conductive metal having a surface; a metal-containing layer in contact with at least part of the conductive metal or alloy surface; and a second liner in the second section of the at least one hole or line, wherein the metal-containing layer forms part of the second liner.
Claim 28
Dependent Claim 65 words
A semiconductor device comprising: a dielectric layer; at least one high aspect ratio submicron hole or line in the dielectric layer; a nonporous liner in the at least one hole or line; a conductive metal or alloy within the liner, the conductive metal or alloy having a surface; and a metal-containing layer in contact with at least part of the conductive metal or alloy surface.
Claim 29
Dependent Claim 65 words
A semiconductor device comprising: a dielectric layer; at least one high aspect ratio submicron hole or line in the dielectric layer; a nonporous liner in the at least one hole or line; a conductive metal or alloy within the liner, the conductive metal or alloy having a surface; and a metal-containing layer in contact with at least part of the conductive metal or alloy surface.
Claim 30
Dependent Claim 139 words
A semiconductor device comprising: a dielectric layer; at least one high aspect ratio submicron hole or line in the dielectric layer, the at least one hole of line having at least first and second sections, wherein at least one of the width, length or height of the first section is different than the width, length or height of the second section; a nonporous first liner in the first section of the at least one hole or line; a first conductive metal of alloy within the first liner, the first conductive metal having a surface; a metal-containing layer in contact with at least part of the conductive metal or alloy surface; and wherein the second nonporous liner in the second section of the at least one hole or line, or in the metal-containing layer forms part of the second liner.
Claim 31
Dependent Claim 139 words
A semiconductor device comprising: a dielectric layer; at least one high aspect ratio submicron hole or line in the dielectric layer, the at least one hole of line having at least first and second sections, wherein at least one of the width, length or height of the first section is different than the width, length or height of the second section; a nonporous first liner in the first section of the at least one hole or line; a first conductive metal of alloy within the first liner, the first conductive metal having a surface; a metal-containing layer in contact with at least part of the conductive metal or alloy surface; and wherein the second nonporous liner in the second section of the at least one hole or line, or in the metal-containing layer forms part of the second liner.

References Cited (Backward Citations)

US3881242A Cited
US3911562A Cited
US4116791A Cited
US4226082A Cited
US4305974A Cited
US4244775A Cited
EP0044372A2 Cited
US4367119A Cited
US4339305A Cited
EP0070737A2 Cited
US4801559A Cited
GB2104290B Cited
EP0077535A1 Cited
US4386116A Cited
US4505025A Cited
US4520041A Cited
EP0127281A1 Cited
US4565157A Cited
US4769686A Cited
US4536249A Cited
US4486946A Cited
US4600624A Cited
US4532702A Cited
US4582563A Cited
US4597826A Cited
EP0150403A1 Cited
US4851295A Cited
US4845050A Cited
US4640004A Cited
US4624864A Cited
US4545852A Cited
US4526631A Cited
US4560436A Cited
US4720908A Cited
US4751197A Cited
US4560435A Cited
US4724060A Cited
US4924281A Cited
US4701349A Cited
US4659427A Cited
US5045916A Cited
EP0195977A2 Cited
US4725566A Cited
US4617087A Cited
US4789648A Cited
US4944836A Cited
US4702792A Cited
EP0224013A2 Cited
US4824802A Cited
US4746219A Cited
US4689113A Cited
US4849079A Cited
EP0247783A2 Cited
EP0254651A1 Cited
US5148259A Cited
EP0261846A1 Cited
US4924295A Cited
US4732658A Cited
US4756810A Cited
US4855798A Cited
US4795722A Cited
US4753709A Cited
US4783248A Cited
EP0279588A2 Cited
US4884123A Cited
US4800176A Cited
US4956313A Cited
EP0305143A2 Cited
EP0312986A1 Cited
US4824544A Cited
US4873565A Cited
US5055906A Cited
US4962414A Cited
US4926237A Cited
US4897709A Cited
EP0338636A1 Cited
US4822753A Cited
EP0343269B1 Cited
US5027185A Cited
US4847111A Cited
US5008730A Cited
US5112693A Cited
US5084417A Cited
US5049975A Cited
US4920073A Cited
US5169685A Cited
US4994162A Cited
US5070391A Cited
US5026470A Cited
CA2035106A1 Cited
US5008217A Cited
US4992135A Cited
US5138432A Cited
US5296404A Cited
US5278449A Cited
US5202579A Cited
US5187119A Cited
US5243222A Cited
US5401675A Cited
US5444018A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-11-14 2004-05-15 2004-11-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-11-14 2008-05-15 2008-11-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-11-14 2012-05-15 2012-11-14 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag