Multilevel metal structure and process for making same

Claim 2

In an integrated circuit package having a substrate with a conductive interconnective first pattern (7a) on a surface thereof, a layered composite structure on the surface of said substrate comprising: a first layer (3') of an organic polymer electrical insulator overlying said surface and said first pattern (7a); and a covering organometallic insulating layer (9) overlying said polymer layer (3'); and a second conductive pattern (7c") on said organometallic insulating layer (9); and there being at least one via opening (10) through said composite layered structure to a portion of said first pattern (7a); and conductive metallurgy (7b') in said via opening (10) interconnecting the said first pattern (7a) and said second pattern (7c').

Claim 3

Structure according to claim 1 wherein the material of said organometallic insulating layer (9) is selected from the group consisting of plasma polymerized divinyl tetramethyl disiloxane, hexamethyl disilazane, divinyltetramethyl disilazane, trivinyl penta methyl trisiloxane, vinyl trimethoxysilane and hexamethyl disiloxane.

Claim 4

Structure according to claim 1 or 2 wherein said organic layer (3') consists of polyimide.

Claim 5

Method of forming superposed levels of metallurgy in the fabrication of an integrated circuit package where said method starts from a substrate having a conductive interconnected pattern (7a) on a surface thereof and comprises the following steps in the following sequence: A) forming a first layer (3') of an electrically insulating polymer on said surface B) coating said first layer (3') with a second layer (9) of a plasma deposited organometallic insulating material divinyl tetramethyl disiloxane, hexamethyl disilazane, hexamethyl disiloxane, divinyl tetramethyl disilazane, trivinyl penta methyl trisiloxane or vinyl trimethoxysilane C) coating said second layer (9) with a third layer (4') of a polymer that is selectively soluble in solvent to which the first said polymer is inert D) coating said third layer (4') with a fourth layer (5') resistant to reactive ion etching in oxygen ambient E) forming on said fourth layer (5') a resist mask (6') defining at least one via opening (10) to a portion of said conductive pattern (7a) F) reactive ion etching in CF 4 ambient the exposed portion of said fourth layer (5') in said via opening (10) G) reactive ion etching in an oxygen ambient portions of said third layer (4') in said via opening (10) H) reactive ion etching in a CF 4 or CHF 3 or mixture of CF 4 and 0 2 ambient the exposed portions of said second layer (9) in said via opening (10) I) reactive ion etching in 0 2 ambient the exposed portion of said first layer (3') in said via opening (10) to expose said portion of said conductive pattern J) blanket coating said substrate inclusive of said via opening (10) with a conductive metal layer (7') having thickness close to the said first layer (3') K) exposing said substrate to said solvent for a time sufficient to remove said third layer (4') and all overlying layers thereon, to expose plasma deposited organometallic insulating layer (9) and said metal via connection (7b) in said via opening (10) L) sequentially coating said plasma deposited organosilicon layer with fifth, sixth and seventh layer (3", 4" or 5" respectively) corresponding respectively to the composition of said first, third and fourth layer (3', 4' or 5' respectively) M) forming a second resist mask (6") having openings (10') corresponding to desired metallurgy patterns (7c) to be deposited on said plasma deposited organosilicon second layer (9), said opening encompassing said via connector (7b') and adjacent discrete areas of said plasma deposited second organosilicon layer (9) N) reactive ion etching in an ambient of CF 4 the exposed portions of said seventh layer (5") in the openings of said second resist mask (6") O) sequentially reactive ion etching in 0 2 ambient said sixth layer (4") and said fifth layer (5") in opening (10') of said second resist mask (6"), to expose said via connector (7b') and adjacent portions of said plasma deposited organosilicon second layer (9) P) depositing a blanket coating of a conductive metal (7") over said substrate inclusive of said via connector (7b') and said adjacent exposed portion of said plasma deposited organosilicon layer (9) Q) exposing said substrate to a solvent selective to the said sixth layer (4") for a time sufficient to remove said sixth layer (4") including overlying layers thereon.

Claim 6

Method of forming superposed levels of metallurgy in the fabrication of an integrated circuit package where said method starts from a substrate having a conductive interconnected pattern (7a) on a surface thereof and comprises the following steps in the following sequence: A) forming a first layer (3') of an electrically insulating polymer on said surface B) coating said first layer (3') with a second layer (9) of a plasma deposited organometallic insulating material divinyl tetramethyl disiloxane, hexamethyl disilazane, hexamethyl disiloxane, divinyl tetramethyl disilazane, trivinyl penta methyl trisiloxane or vinyl trimethoxysilane C) coating said second layer (9) with a third layer (4') of a polymer that is selectively soluble in solvent to which the first said polymer is inert D) coating said third layer (4') with a fourth layer (5') resistant to reactive ion etching in oxygen ambient E) forming on said fourth layer (5') a resist mask (6') defining at least one via opening (10) to a portion of said conductive pattern (7a) F) reactive ion etching in CF 4 ambient the exposed portion of said fourth layer (5') in said via opening (10) G) reactive ion etching in an oxygen ambient portions of said third layer (4') in said via opening (10) H) reactive ion etching in a CF 4 or CHF 3 or mixture of CF 4 and 0 2 ambient the exposed portions of said second layer (9) in said via opening (10) I) reactive ion etching in 0 2 ambient the exposed portion of said first layer (3') in said via opening (10) to expose said portion of said conductive pattern J) blanket coating said substrate inclusive of said via opening (10) with a conductive metal layer (7') having thickness close to the said first layer (3') K) exposing said substrate to said solvent for a time sufficient to remove said third layer (4') and all overlying layers thereon, to expose plasma deposited organometallic insulating layer (9) and said metal via connection (7b) in said via opening (10) L) sequentially coating said plasma deposited organosilicon layer with fifth, sixth and seventh layer (3", 4" or 5" respectively) corresponding respectively to the composition of said first, third and fourth layer (3', 4' or 5' respectively) M) forming a second resist mask (6") having openings (10') corresponding to desired metallurgy patterns (7c) to be deposited on said plasma deposited organosilicon second layer (9), said opening encompassing said via connector (7b') and adjacent discrete areas of said plasma deposited second organosilicon layer (9) N) reactive ion etching in an ambient of CF 4 the exposed portions of said seventh layer (5") in the openings of said second resist mask (6") O) sequentially reactive ion etching in 0 2 ambient said sixth layer (4") and said fifth layer (5") in opening (10') of said second resist mask (6"), to expose said via connector (7b') and adjacent portions of said plasma deposited organosilicon second layer (9) P) depositing a blanket coating of a conductive metal (7") over said substrate inclusive of said via connector (7b') and said adjacent exposed portion of said plasma deposited organosilicon layer (9) Q) exposing said substrate to a solvent selective to the said sixth layer (4") for a time sufficient to remove said sixth layer (4") including overlying layers thereon.

Claim 7

Method according to claim 4 wherein multiple interconnecting levels of metallurgy are formed by repeating the sequence of process steps A through Q.

Claim 8

Method according to claim 4 or 5 wherein said first layer (3') is a polyimide.

Claim 9

Method according to any one of claims 4 to 6, wherein the material for forming the second layer (9) is selected from the group consisting of divinyl tetramethyl disiloxane, hexamethyl disilazane, hexamethyl disiloxane, divinyl tetramethyl disilazane, trivinyl penta methyl trisiloxane or vinyl trimethoxysilane.

Claim 10

Method according to any one of claims 4 to 7 wherein said third layer (4') is a polysulfone.

Claim 11

Method according to any one of claims 4 to 8 wherein said fourth layer (5') is SiO x or plasma deposited organosilicon.

Claim 12

Method according to any one of claims 4 to 9 wherein said conductive metal (7', 7") is an aluminum copper alloy.