Planar multi-level metal-insulator structure comprising a substrate, a conductive interconnection pattern and a superposed conductive structure and a method to form such a structure

Claim 2

Package comprising a substrate having a conductive interconnected pattern on a surface thereof and a superposed conductive structure including an insulating layer on said pattern with at least one via opening, a second conductive pattern (50A, 50B) on said insulating layer, said via opening being filled with conductive means connecting the conductive interconnected pattern and the second conductive pattern (50A, 50B), characterized in that said insulating layer comprises a composite layer consisting of a lower layer (30) of an electrically insulating organic polymer overlying said surface and said conductive interconnected pattern and a covering oxygen plasma resistant in organic insulating layer overlying said polymer layer.

Claim 3

Package according to claim 1, wherein said inorganic insulating layer is silicon nitride.

Claim 4

Package according to claim 1 or 2, wherein said polymer is a polyimide.

Claim 5

Package according to any one of claim 1 to 3, wherein the substrate is a silicon semiconductor device, especially an integrated circuit semiconductor device having active and passive devices and an overlying insulating layer with contact openings to said devices, a ceramic or a glass-ceramic substrate, or the package as defined in claim 1 but without the second conductive pattern (50A, 50B).

Claim 6

Method of forming superposed levels of metallurgy in the fabrication of a package particularly according to any one of claims 1 to 4, comprised of a substrate having a conductive interconnected pattern (26) on a surface thereof, including the steps: forming a first layer (30) of an electrically insulating polymer on said surface, coating said first layer (30) with a third layer (32) of a polymer that is selectively soluble in a solvent substantially inert to the first said polymer, coating said third layer (32) with a fourth layer (34) resistant to reactive ion etching in oxygen, forming on said fourth layer (34) a resist mask defining at least one via opening to a portion of said conductive pattern (26), reactive ion etching in an CF 4 ambient the exposed portion of said fourth layer (34) in said via opening (36), reactive ion etching in an 0 2 ambient the exposed portions of said third layer (32) and of said first layer (30) in said via opening (36) to expose said portion of said conductive pattern (26), blanket coating the then existing structure inclusive of said via opening (36) with a conductive metal layer (38), exposing the structure to said solvent for a time sufficient to remove said third layer (32) and all overlying layers thereon, sequentially depositing on the then existing structure fifth, sixth and seventh layers (42, 43 or 44 respectively), corresponding, respectively to the compositions of said first, third and fourth layers (30, 32 or 34 respectively), forming a second resist mask having openings corresponding to the desired second conductive pattern (50A, 50B) to be deposited, reactive ion etching in an CF 4 ambient the exposed portions of said seventh layer (44) in the openings (41) of said second resist mask, sequentially removing by reactive ion etching in an 0 2 ambient said sixth layer (43) and said fifth layer (42) in the openings (41) of said second resist mask, blanket depositing a layer (40) of a conductive metal and exposing the then existing structure to a solvent selective to the sixth layer (43) for a time sufficient to remove said sixth layer (43) and all overlying layers thereon, characterized in that prior to the deposition of a third layer (32) a second layer (23) of silicon nitride is deposited, that prior to the reactive ion etching of the first layer (30) in an 0 2 ambient the exposed portion of silicon nitride layer (23) is reactive ion etched in an CF 4 ambient said metal layer (38) coating the then existing structure inclusive said via opening (36) is deposited in a thickness of said first and second layer (30 and 23, respectively) and that the second layer (23) is used as etch stop layer in the reactive ion etching of layers (43) and (42).

Claim 7

Method according to claim 5, wherein multiple interconnection metallurgy levels are formed by repeating the sequence of process steps of claim 5 once or several times.

Claim 8

Method according to claim 5 or 6, wherein said third layer (32) is a polysulfone.

Claim 9

Method according to any one of claims 5 to 7, wherein said fourth layer (34) is SiO or a glass resin polymer comprised predominantly of polymethyl- siloxane.

Claim 10

Method according to any one of claims 5 to 8, wherein said conductive metal is an aluminum copper alloy.