US4824802A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of filling interlevel dielectric via or contact holes in multilevel VLSI metallization structures
Assignee: Intersil Corp
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Filing: 1987-10-02
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Granted: 1989-04-25
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Expires: 2007-10-02
Abstract
Abstract A method compatible with very large scale integrated circuit fabrication processes is employed to provide an electrical connection between conductive layers separated by an insulative layer in integrated circuit devices. An intermediary metal such as molybdenum or tungsten is deposited by one or more methods so as to fill an opening in the insulative layer. A planarization resist may be applied on the substrate and the resulting configuration is planarizingly etched down to the insulative layer so as to provide a metal plug conductive layers. Deposition is by sputtering, evaporation, or by either selective or non-selective chemical vapor deposition. The process and structure provided herein significantly alleviates step coverage problems associated with aluminum and like materials which do not readily penetrate small VLSI circuit openings.
Inventors
- 👤 Dale M. Brown
- 👤 Bernard Gorowitz
- 👤 Richard J. Saia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:42
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/062; H10W20/056
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
124 words
A method of forming an electrical connection to a conductive layer underlying an insulative layer on an integrated circuit substrate, said method comprising the steps of: forming an opening in said insulative layer so as to expose an underlying portion of said conductive layer through said opening; selectively depositing an intermediary metal in said opening so that said intermediary metal substantially fills said opening and extends over said insulative layer only in the vicinity of said opening; applying and flowing a planarization resist over said substrate; and planarizingly etching said resist and said intermediary metal down to said insulative layer by reactive ion etching or plasma etching, whereby said opening is provided with a metal plug in electrical contact with said underlying conductive layer.
Claim 2
Independent Claim
124 words
A method of forming an electrical connection to a conductive layer underlying an insulative layer on an integrated circuit substrate, said method comprising the steps of: forming an opening in said insulative layer so as to expose an underlying portion of said conductive layer through said opening; selectively depositing an intermediary metal in said opening so that said intermediary metal substantially fills said opening and extends over said insulative layer only in the vicinity of said opening; applying and flowing a planarization resist over said substrate; and planarizingly etching said resist and said intermediary metal down to said insulative layer by reactive ion etching or plasma etching, whereby said opening is provided with a metal plug in electrical contact with said underlying conductive layer.
Claim 3
Dependent Claim
24 words
The method of claim 1 further including the step of disposing a conductive layer over said opening and in contact with said intermediary metal.
Claim 4
Dependent Claim
21 words
The method of claim 1 in which said intermediary metal comprises material selected from the group consisting of molybdenum and tungsten.
Claim 5
Dependent Claim
16 words
The method of claim 1 in which said intermediary metal is deposited by chemical vapor deposition.
Claim 6
Dependent Claim
22 words
The method of claim 1 in which said resist comprises material selected from the group consisting of azoquinone-novalac-type photoresists, polymethylmethacrylates and polyimides.
Claim 7
Dependent Claim
20 words
The method of claim 1 in which said resist and said intermediary metal are etched at substantially the same rate.
Claim 8
Dependent Claim
12 words
The method of claim 1 in which said etching is plasma etching.
Claim 9
Dependent Claim
13 words
The method of claim 1 in which said etching is reactive ion etching.
References Cited (Backward Citations)
US4520041A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-24 | 1992-10-24 | 1993-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-24 | 1996-10-24 | 1997-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-24 | 2000-10-24 | 2001-04-25 | $7700.00 | Window Closed / Lapsed |