Patent US5889328A successfully refreshed from Google Patents.
US5889328A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Refractory metal capped low resistivity metal conductor lines and vias
Assignee: GlobalFoundries Inc
•
Filing: 1996-12-03
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Granted: 1999-03-30
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Expires: 2016-12-03
Abstract
Abstract Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH4 to WF6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1 mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1 mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.
Inventors
- 👤 Rajiv V. Joshi
- 👤 Jerome J. Cuomo
- 👤 Hormazdyar M. Dalal
- 👤 Louis L. Hsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 12:33
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/033; H10P; H10P14/00; H10P14/40; H10P14/42; H10P14/43; H10P14/44; H10W20/036; H10W20/037; H10W20/038; H10W20/039; H10W20/056; H10W20/062; H10W20/40; H10W20/41; H10W20/425; H10W20/44; H10W20/4403; H10W20/4421; H10W20/4424; H10W70/00; H10W70/60; H10W70/62; H10W70/66; Y; Y10; Y10S; Y10S148/00; Y10S148/015; Y10S257/00; Y10S257/915; Y10S438/00; Y10S438/959
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
69 words
A semiconductor device comprising: a dielectric layer; at least one high aspect ratio submicron hole or line in the dielectric layer, the at least one hole or line having sidewalls and a bottom; and a liner in the at least one hole or line, the liner being substantially conformal with the thickness of the liner on the bottom being greater than the thickness of the liner on the sidewalls.
Claim 2
Dependent Claim
69 words
A semiconductor device comprising: a dielectric layer; at least one high aspect ratio submicron hole or line in the dielectric layer, the at least one hole or line having sidewalls and a bottom; and a liner in the at least one hole or line, the liner being substantially conformal with the thickness of the liner on the bottom being greater than the thickness of the liner on the sidewalls.
Claim 3
Dependent Claim
16 words
The semiconductor device of claim 1 further comprising a conductive metal or alloy in the liner.
Claim 4
Dependent Claim
26 words
The semiconductor device of claim 1 wherein the liner is present in an amount effective to promote adhesion of a metal or alloy to the liner.
Claim 5
Dependent Claim
15 words
The semiconductor device of claim 1 wherein the liner comprises a refractory metal or alloy.
Claim 6
Dependent Claim
20 words
The semiconductor device of claim 1 wherein the aspect ratio of the hole or line is greater than about 2:1.
Claim 7
Dependent Claim
32 words
The semiconductor device of claim 1 wherein the ratio of the thickness of the liner on the bottom to the thickness of the liner on the sidewalls is at least about 4:3.
Claim 8
Dependent Claim
32 words
The semiconductor device of claim 1 wherein the ratio of the thickness of the liner on the bottom to the thickness of the liner on the sidewalls is at least about 1.5:1.
Claim 9
Dependent Claim
12 words
The semiconductor device of claim 1 wherein the liner is substantially homogeneous.
Claim 10
Dependent Claim
79 words
A semiconductor device comprising: a dielectric layer; at least one submicron hole or line in the dielectric layer, the at least one hole or line having sidewalls and a bottom and an aspect ratio of at least 2:1; and a liner in the at least one hole or line, the liner being substantially conformal with the ratio of the thickness of the liner on the bottom to the thickness of the liner on the sidewalls being at least 4:3.
Claim 11
Dependent Claim
79 words
A semiconductor device comprising: a dielectric layer; at least one submicron hole or line in the dielectric layer, the at least one hole or line having sidewalls and a bottom and an aspect ratio of at least 2:1; and a liner in the at least one hole or line, the liner being substantially conformal with the ratio of the thickness of the liner on the bottom to the thickness of the liner on the sidewalls being at least 4:3.
Claim 12
Dependent Claim
16 words
The semiconductor device of claim 9 further comprising a conductive metal or alloy in the liner.
Claim 13
Dependent Claim
15 words
The semiconductor device of claim 9 wherein the liner comprises a refractory metal or alloy.
Claim 14
Dependent Claim
32 words
The semiconductor device of claim 9 wherein the ratio of the thickness of the liner on the bottom to the thickness of the liner on the sidewalls is at least about 1.5:1.
Claim 15
Dependent Claim
12 words
The semiconductor device of claim 9 wherein the liner is substantially homogeneous.
Claim 16
Dependent Claim
70 words
A semiconductor device comprising: a dielectric layer; at least one high aspect ratio submicron hole or line in the dielectric layer, the at least one hole or line having sidewalls and a bottom; and a sputtered liner in the at least one hole or line, the liner being substantially conformal with the thickness of the liner on the bottom being greater than the thickness of the liner on the sidewalls.
Claim 17
Dependent Claim
70 words
A semiconductor device comprising: a dielectric layer; at least one high aspect ratio submicron hole or line in the dielectric layer, the at least one hole or line having sidewalls and a bottom; and a sputtered liner in the at least one hole or line, the liner being substantially conformal with the thickness of the liner on the bottom being greater than the thickness of the liner on the sidewalls.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-29 | 2002-09-28 | 2003-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-29 | 2006-09-28 | 2007-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-29 | 2010-09-28 | 2011-03-30 | $7700.00 | Window Closed / Lapsed |