US7221017B2
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US
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Memory utilizing oxide-conductor nanolaminates
Assignee: Micron Technology Inc
•
Filing: 2002-07-08
•
Granted: 2007-05-22
•
Expires: 2022-07-08
Abstract
Abstract Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A floating gate is separated from the channel region by a first gate oxide. The floating gate includes oxide-conductor nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-conductor nanolaminate layers.
Inventors
- 👤 Leonard Forbes
- 👤 Kie Y. Ahn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:12
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5671; H; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D30/6891; H10D30/6893; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
104 words
A floating gate transistor, comprising: a first source/drain region; a second source/drain region; a channel region between the first and the second source/drain regions; a floating gate separated from the channel region by a first oxide layer, wherein the floating gate region includes oxide-conductor nanolaminate layers, wherein the nanolaminate layers include a layer of a metal conductor formed using an atomic layer deposition process; a control gate separated from the floating gate by a second oxide layer; and circuitry coupled to the floating gate transistor to program the floating gate in a reverse direction, and to read the floating gate in a forward direction.
Claim 2
Dependent Claim
104 words
A floating gate transistor, comprising: a first source/drain region; a second source/drain region; a channel region between the first and the second source/drain regions; a floating gate separated from the channel region by a first oxide layer, wherein the floating gate region includes oxide-conductor nanolaminate layers, wherein the nanolaminate layers include a layer of a metal conductor formed using an atomic layer deposition process; a control gate separated from the floating gate by a second oxide layer; and circuitry coupled to the floating gate transistor to program the floating gate in a reverse direction, and to read the floating gate in a forward direction.
Claim 3
Dependent Claim
17 words
The floating gate transistor of claim 1 , wherein the oxide-conductor nanolaminate layers include Tantalum Nitride (TaN).
Claim 4
Dependent Claim
17 words
The floating gate transistor of claim 1 , wherein the oxide-conductor nanolaminate layers include Titanium Nitride (TiN).
Claim 5
Dependent Claim
17 words
The floating gate transistor of claim 1 , wherein the oxide-conductor nanolaminate layers include Tungsten Nitride (WN).
Claim 6
Dependent Claim
17 words
The floating gate transistor of claim 1 , wherein the oxide-conductor nanolaminate layers include Niobium Nitride (NbN).
Claim 7
Dependent Claim
17 words
The floating gate transistor of claim 1 , wherein the oxide-conductor nanolaminate layers include Molybdenum Nitride (MoN).
Claim 8
Dependent Claim
16 words
The floating gate transistor of claim 1 , wherein the oxide-conductor nanolaminate layers include Zinc-Oxide-Silicon (ZnOS).
Claim 9
Dependent Claim
15 words
The floating gate transistor of claim 1 , wherein the metal conductor includes Tungsten (W).
Claim 10
Dependent Claim
16 words
The floating gate transistor of claim 1 , wherein the oxide-conductor nanolaminate layers include Nickel (Ni).
Claim 11
Dependent Claim
199 words
A floating gate transistor array, comprising: a number of floating gate transistor cells formed on a substrate, wherein each floating gate transistor cell includes a source region, a drain region, a channel region between the source and the drain regions, and a floating gate separated from the channel region by a first gate oxide, and a control gate separated from the floating gate by a second gate oxide, and wherein the floating gate region includes oxide-conductor nanolaminate layers, wherein the nanolaminate layers include a layer of a metal conductor formed using an atomic layer deposition process; a number of bit lines coupled to the drain region of each floating gate transistor cell along rows of the floating gate transistor array; a number of word lines coupled to the control gate of each floating gate transistor cell along columns of the memory array; a number of sourcelines, wherein the source region of each floating gate transistor cell is coupled to the number of sourcelines along rows of the floating gate transistor cells; and circuitry coupled to at least one transistor cell to program the transistor cell in a reverse direction, and to read the transistor cell in a forward direction.
Claim 12
Dependent Claim
199 words
A floating gate transistor array, comprising: a number of floating gate transistor cells formed on a substrate, wherein each floating gate transistor cell includes a source region, a drain region, a channel region between the source and the drain regions, and a floating gate separated from the channel region by a first gate oxide, and a control gate separated from the floating gate by a second gate oxide, and wherein the floating gate region includes oxide-conductor nanolaminate layers, wherein the nanolaminate layers include a layer of a metal conductor formed using an atomic layer deposition process; a number of bit lines coupled to the drain region of each floating gate transistor cell along rows of the floating gate transistor array; a number of word lines coupled to the control gate of each floating gate transistor cell along columns of the memory array; a number of sourcelines, wherein the source region of each floating gate transistor cell is coupled to the number of sourcelines along rows of the floating gate transistor cells; and circuitry coupled to at least one transistor cell to program the transistor cell in a reverse direction, and to read the transistor cell in a forward direction.
Claim 13
Dependent Claim
18 words
The floating gate transistor array of claim 10 , wherein the oxide-conductor nanolaminate layers include Tantalum Nitride (TaN).
Claim 14
Dependent Claim
17 words
The floating gate transistor of claim 10 , wherein the oxide-conductor nanolaminate layers include Titanium Nitride (TiN).
Claim 15
Dependent Claim
18 words
The floating gate transistor array of claim 10 , wherein the oxide-conductor nanolaminate layers include Tungsten Nitride (WN).
Claim 16
Dependent Claim
18 words
The floating gate transistor array of claim 10 , wherein the oxide-conductor nanolaminate layers include Niobium Nitride (NbN).
Claim 17
Dependent Claim
18 words
The floating gate transistor array of claim 10 , wherein the oxide-conductor nanolaminate layers include Molybdenum Nitride (MoN).
Claim 18
Dependent Claim
17 words
The floating gate transistor array of claim 10 , wherein the oxide-conductor nanolaminate layers include Zinc-Oxide-Silicon (ZnOS).
Claim 19
Dependent Claim
16 words
The floating gate transistor array of claim 10 , wherein the metal conductor includes Tungsten (W).
Claim 20
Dependent Claim
17 words
The floating gate transistor array of claim 10 , wherein the oxide-conductor nanolaminate layers include Nickel (Ni).
Claim 21
Dependent Claim
219 words
A floating gate transistor array, comprising: a number of floating gate transistor cells formed on a substrate, wherein each floating gate transistor cell includes a source region, a drain region, a channel region between the source and the drain regions, and a floating gate separated from the channel region by a first gate oxide, and a control gate separated from the floating gate by a second gate oxide, and wherein the floating gate region includes oxide-conductor nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-conductor nanolaminate layers; a number of bit lines coupled to the drain region of each floating gate transistor cell along rows of the floating gate transistor array; a number of word lines coupled to the control gate of each floating gate transistor cell along columns of the memory array; a number of sourcelines, wherein the source region of each floating gate transistor cell is coupled to the number of sourcelines along rows of the floating gate transistor cells; and wherein at least one of floating gate transistor cells is a programmed floating gate transistor having one of a number of charge levels trapped in the floating gate, wherein the one of a number of charge levels trapped in the floating gate includes a charge of approximately 100 electrons.
Claim 22
Dependent Claim
219 words
A floating gate transistor array, comprising: a number of floating gate transistor cells formed on a substrate, wherein each floating gate transistor cell includes a source region, a drain region, a channel region between the source and the drain regions, and a floating gate separated from the channel region by a first gate oxide, and a control gate separated from the floating gate by a second gate oxide, and wherein the floating gate region includes oxide-conductor nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-conductor nanolaminate layers; a number of bit lines coupled to the drain region of each floating gate transistor cell along rows of the floating gate transistor array; a number of word lines coupled to the control gate of each floating gate transistor cell along columns of the memory array; a number of sourcelines, wherein the source region of each floating gate transistor cell is coupled to the number of sourcelines along rows of the floating gate transistor cells; and wherein at least one of floating gate transistor cells is a programmed floating gate transistor having one of a number of charge levels trapped in the floating gate, wherein the one of a number of charge levels trapped in the floating gate includes a charge of approximately 100 electrons.
Claim 23
Dependent Claim
42 words
The floating gate transistor array of claim 19 , the number of floating gate transistor cells is configured as active devices with gain to provide amplification of stored charge from 100 to 800,000 electrons over a read address period of 10 nS.
Claim 24
Dependent Claim
44 words
The floating gate transistor array of claim 19 , wherein the number of floating gate transistor cells extending from a substrate operate as equivalent to a floating gate transistor having a size equal to or less than 2.0 lithographic feature squared (2F 2 ).
Claim 25
Dependent Claim
191 words
A programmable logic array, comprising: a plurality of input lines for receiving an input signal; a plurality of output lines; and one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to a received input signal, wherein each logic cell includes a floating gate transistor cell including: a first source/drain region; a second source/drain region; a channel region between the first and the second source/drain regions; a floating gate separated from the channel region by a first gate oxide, wherein the floating gate region includes oxide-conductor nanolaminate layers, wherein the nanolaminate layers include a layer of a metal conductor formed using an atomic layer deposition process; a control gate separated from the floating gate by a second gate oxide; and circuitry coupled to the floating gate transistor cell to program the floating gate in a reverse direction, and to read the floating gate in a forward direction.
Claim 26
Dependent Claim
191 words
A programmable logic array, comprising: a plurality of input lines for receiving an input signal; a plurality of output lines; and one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to a received input signal, wherein each logic cell includes a floating gate transistor cell including: a first source/drain region; a second source/drain region; a channel region between the first and the second source/drain regions; a floating gate separated from the channel region by a first gate oxide, wherein the floating gate region includes oxide-conductor nanolaminate layers, wherein the nanolaminate layers include a layer of a metal conductor formed using an atomic layer deposition process; a control gate separated from the floating gate by a second gate oxide; and circuitry coupled to the floating gate transistor cell to program the floating gate in a reverse direction, and to read the floating gate in a forward direction.
Claim 27
Dependent Claim
17 words
The programmable logic array of claim 22 , wherein the oxide-conductor nanolaminate layers include Tantalum Nitride (TaN).
Claim 28
Dependent Claim
17 words
The programmable logic array of claim 22 , wherein the oxide-conductor nanolaminate layers include Titanium Nitride (TiN).
Claim 29
Dependent Claim
17 words
The programmable logic array of claim 22 , wherein the oxide-conductor nanolaminate layers include Tungsten Nitride (WN).
Claim 30
Dependent Claim
17 words
The programmable logic array of claim 22 , wherein the oxide-conductor nanolaminate layers include Niobium Nitride (NbN).
Claim 31
Dependent Claim
17 words
The programmable logic array of claim 22 , wherein the oxide-conductor nanolaminate layers include Molybdenum Nitride (MoN).
Claim 32
Dependent Claim
16 words
The programmable logic array of claim 22 , wherein the oxide-conductor nanolaminate layers include Zinc-Oxide-Silicon (ZnOS).
Claim 33
Dependent Claim
15 words
The programmable logic array of claim 22 , wherein the metal conductor includes Tungsten (W).
Claim 34
Dependent Claim
16 words
The programmable logic array of claim 22 , wherein the oxide-conductor nanolaminate layers include Nickel (Ni).
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