US6545314B2
Expired / Lapsed
US
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Memory using insulator traps
Assignee: Micron Technology Inc
•
Filing: 2001-05-15
•
Granted: 2003-04-08
•
Expires: 2021-05-15
Abstract
Abstract A memory cell provides point defect trap sites in an insulator for storing data charges. Single electrons are stored on respective point defect trap sites and a resulting parameter, such as transistor drain current, is detected. By adjusting the density of the point defect trap sites, more uniform step changes in drain current are obtained as single electrons are stored on or removed from respective trap sites. By also adjusting the trapping energy of the point defect trap sites, the memory cell provides either volatile data storage, similar to a dynamic random access memory (DRAM), or nonvolatile data storage, similar to an electrically erasable and programmable read only memory (EEPROM). The memory cell is used for storing binary or multi-state data.
Inventors
- 👤 Leonard Forbes
- 👤 Joseph E. Geusic
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:12
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5671; B; B82; B82Y; B82Y10/00; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; G11C16/0458; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/687; H10D30/688; G11C2216/00; G11C2216/02; G11C2216/08; H10D30/69; H10D30/691
Claims Analysis
Total Claims: 51
Claim 1
Independent Claim
99 words
A computer system, the computer system comprising a memory device, the memory device including: an array of memory cells, at least one of the memory cells including a transistor in which a gate insulator carries trap sites at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 2
Dependent Claim
99 words
A computer system, the computer system comprising a memory device, the memory device including: an array of memory cells, at least one of the memory cells including a transistor in which a gate insulator carries trap sites at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 3
Dependent Claim
85 words
A memory device, comprising: an array of memory cells, each memory cell including a transistor in which a gate insulator cries trap sites at a density such that the trap sites arc substantially shielded from each other by intervening portions of the insulator; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuitry coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 4
Dependent Claim
85 words
A memory device, comprising: an array of memory cells, each memory cell including a transistor in which a gate insulator cries trap sites at a density such that the trap sites arc substantially shielded from each other by intervening portions of the insulator; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuitry coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 5
Dependent Claim
30 words
The memory device of claim 2 , further comprising a write/erase circuit coupled to the memory cell array and writing data to memory cells in the array of memory cells.
Claim 6
Dependent Claim
21 words
The memory device of claim 2 , wherein the write/erase circuit stores electrons on the trap sites by hot electron injection.
Claim 7
Dependent Claim
20 words
The memory device of claim 2 , wherein the write/erase circuit removes electrons from the trap sites by Price-Sat tunneling.
Claim 8
Dependent Claim
35 words
The memory device of claim 2 , wherein the trap sites are carried in the gate insulator at an real concentration that is approximately between 10 12 and 10 15 trap sites per square centimeter.
Claim 9
Dependent Claim
106 words
A memory device comprising: an array of memory cells, at least one memory cell of which includes a transistor in which a gate insulator carries point defect trap sites at a density such that die trap sites are substantially insulated from each other by intervening portions of the insulator and wherein the trap sites are each capable of capturing no more than one electron; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 10
Dependent Claim
106 words
A memory device comprising: an array of memory cells, at least one memory cell of which includes a transistor in which a gate insulator carries point defect trap sites at a density such that die trap sites are substantially insulated from each other by intervening portions of the insulator and wherein the trap sites are each capable of capturing no more than one electron; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 11
Dependent Claim
25 words
The memory device of claim 7 , wherein the trap sites have an effective cross-sectional area of capture of approximately 10 −15 cm 2 .
Claim 12
Dependent Claim
32 words
The memory device of claim 7 , wherein the trap sites have a retention time of approximately between 1 second and 3 million years at a temperature of approximately 85 degrees Celsius.
Claim 13
Dependent Claim
34 words
The memory device of claim 7 , wherein the trap sites are carried in the insulator at an areal concentration tat is approximately between 10 12 and 10 15 trap sites per square centimeter.
Claim 14
Dependent Claim
22 words
The memory device of claim 7 , wherein ones of the trap sites do not substantially overlap others of the trap sites.
Claim 15
Dependent Claim
46 words
The memory device of claim 7 , wherein the insulator is formed on a substrate, and the insulator has a thickness, and the trap sites are carried in the insulator at a distance from the substrate that is approximately ⅓ of a thickness of the insulator.
Claim 16
Dependent Claim
108 words
A memory device, comprising: an array of memory cells, at least one of the memory cells including at least one transistor in which a gate insulator carries trap sites at a density such that the trap sites arc substantially insulated from each other by intervening portions of the insulator and wherein the trap sites have a trapping energy of approximately between 1.3 ev and 2.4 eV; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 17
Dependent Claim
108 words
A memory device, comprising: an array of memory cells, at least one of the memory cells including at least one transistor in which a gate insulator carries trap sites at a density such that the trap sites arc substantially insulated from each other by intervening portions of the insulator and wherein the trap sites have a trapping energy of approximately between 1.3 ev and 2.4 eV; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 18
Dependent Claim
34 words
The memory device of claim 13 , wherein the trap sites are carried in the insulator at an areal concentration that is approximately between 10 12 and 10 15 trap sites per square centimeter.
Claim 19
Dependent Claim
22 words
The memory device of claim 13 , wherein ones of the trap sites do not substantially overlap others of the trap sites.
Claim 20
Dependent Claim
107 words
A memory device, comprising: an array of memory cells, at least one memory cell comprising an insulator carrying trap sites at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator, wherein the insulator is selected from a group consisting essentially of amorphous silicon dioxide, quartz, aluminum trioxide, titanium dioxide, lithium niobate, silicon nitride, and diamond; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 21
Dependent Claim
107 words
A memory device, comprising: an array of memory cells, at least one memory cell comprising an insulator carrying trap sites at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator, wherein the insulator is selected from a group consisting essentially of amorphous silicon dioxide, quartz, aluminum trioxide, titanium dioxide, lithium niobate, silicon nitride, and diamond; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 22
Dependent Claim
34 words
The memory device of claim 16 , wherein the trap sites are carried in the insulator at an areal concentration that is approximately between 10 12 and 10 15 trap sites per square centimeter.
Claim 23
Dependent Claim
22 words
The memory device of claim 16 , wherein ones of the trap sites do not substantially overlap others of the trap sites.
Claim 24
Dependent Claim
41 words
A memory device comprising an insulator carrying point defect trap sites that are electrically isolated from each other by intervening portions of the insulator wherein the trap sites have a trapping energy of between approximately 1.3 eV and approximately 2.4 eV.
Claim 25
Dependent Claim
41 words
A memory device comprising an insulator carrying point defect trap sites that are electrically isolated from each other by intervening portions of the insulator wherein the trap sites have a trapping energy of between approximately 1.3 eV and approximately 2.4 eV.
Claim 26
Dependent Claim
24 words
The memory device of claim 19 , wherein the trap sites have a cross-sectional area of capture of approximately 10 −15 cm 2 .
Claim 27
Dependent Claim
31 words
The memory device of claim 19 , wherein the trap sites have a retention time of approximately between 1 second and 3 million years at a temperature of 85 degrees Celsius.
Claim 28
Dependent Claim
33 words
The memory device claim 19 , wherein the trap sites are carried in the insulator at an areal concentration that is approximately between 10 12 and 10 15 trap sites per square centimeter.
Claim 29
Dependent Claim
46 words
The memory device of claim 19 , wherein the insulator is formed on a substrate, and the insulator has a thickness, and the trap sites are carried in the insulator at a distance from the substrate that is approximately ⅓ of a thickness of the insulator.
Claim 30
Dependent Claim
107 words
A memory device, comprising: an array of memory cells, at least one memory cell including a transistor in which a gate insulator carries point defect trap sites that are electrically isolated from each other by intervening portions of the insulator wherein the insulator is selected from a group consisting essentially of amorphous silicon dioxide, quartz, aluminum trioxide, titanium dioxide, lithium niobate, silicon nitride, and diamond; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 31
Dependent Claim
107 words
A memory device, comprising: an array of memory cells, at least one memory cell including a transistor in which a gate insulator carries point defect trap sites that are electrically isolated from each other by intervening portions of the insulator wherein the insulator is selected from a group consisting essentially of amorphous silicon dioxide, quartz, aluminum trioxide, titanium dioxide, lithium niobate, silicon nitride, and diamond; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 32
Dependent Claim
36 words
The memory cell of claim 24 , wherein the trap sites are carried by the insulator at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator.
Claim 33
Dependent Claim
20 words
The memory cell of claim 24 , wherein the trap sites are capable of capturing no more than one electron.
Claim 34
Dependent Claim
24 words
The memory cell of claim 24 , wherein the trap sites have a cross-sectional area of capture of approximately 10 −15 cm 2 .
Claim 35
Dependent Claim
137 words
A memory device, comprising: an array of memory cells, at least one of the memory cells including a transistor, the transistor including a source, a drain, a channel region between the source and drain, a control gate, an insulator between the control gate and the channel region, and a floating gate wherein the floating gate includes point defect trap sites that arc carried by the insulator and electrically isolated from each other by intervening portions of the insulator and wherein the trap sites have a trapping energy of approximately between 1.3 ev and 2.4 ev; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 36
Dependent Claim
137 words
A memory device, comprising: an array of memory cells, at least one of the memory cells including a transistor, the transistor including a source, a drain, a channel region between the source and drain, a control gate, an insulator between the control gate and the channel region, and a floating gate wherein the floating gate includes point defect trap sites that arc carried by the insulator and electrically isolated from each other by intervening portions of the insulator and wherein the trap sites have a trapping energy of approximately between 1.3 ev and 2.4 ev; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 37
Dependent Claim
31 words
The memory device of claim 28 , wherein the trap sites have a retention time of approximately between 1 second and 3 million years at a temperature of 85 degrees Celsius.
Claim 38
Dependent Claim
147 words
A memory cell, comprising: an array of memory cells, at least one of the memory cells including a transistor, the transistor including a source, a drain, a channel region between the source and drain, a control gate, an insulator between the control gate and the channel region, and a floating gate and wherein the floating gate includes point defect trap sites that are carried by the insulator and electrically isolated from each other by intervening portions of the insulator and wherein the insulator is selected from a group consisting essentially of amorphous silicon dioxide, quartz, aluminum trioxide, titanium dioxide, lithium niobate, silicon nitride, and diamond; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 39
Dependent Claim
147 words
A memory cell, comprising: an array of memory cells, at least one of the memory cells including a transistor, the transistor including a source, a drain, a channel region between the source and drain, a control gate, an insulator between the control gate and the channel region, and a floating gate and wherein the floating gate includes point defect trap sites that are carried by the insulator and electrically isolated from each other by intervening portions of the insulator and wherein the insulator is selected from a group consisting essentially of amorphous silicon dioxide, quartz, aluminum trioxide, titanium dioxide, lithium niobate, silicon nitride, and diamond; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 40
Dependent Claim
19 words
The memory device of claim 30 wherein the trap sites are capable of accepting no more than one electron.
Claim 41
Dependent Claim
159 words
A memory device, comprising: an array of memory cells, at least one memory cell of which includes a transistor, the transistor includes a source, a drain, a channel region between the source and drain, a control gate, an insulator between the control gate and the channel region, and a floating gate and wherein the floating gate includes point defect trap sites that are carried by the insulator and electrically isolated from each other by intervening portions of the insulator and wherein the insulator has a thickness between the control gate and the channel region, and the point defects are disposed at a distance from the channel region that is approximately ⅓ of the thickness or the insulator; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 42
Dependent Claim
159 words
A memory device, comprising: an array of memory cells, at least one memory cell of which includes a transistor, the transistor includes a source, a drain, a channel region between the source and drain, a control gate, an insulator between the control gate and the channel region, and a floating gate and wherein the floating gate includes point defect trap sites that are carried by the insulator and electrically isolated from each other by intervening portions of the insulator and wherein the insulator has a thickness between the control gate and the channel region, and the point defects are disposed at a distance from the channel region that is approximately ⅓ of the thickness or the insulator; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 43
Dependent Claim
19 words
The memory device of claim 32 wherein the trap sites are capable of capturing no more than one electron.
Claim 44
Dependent Claim
147 words
A memory device, comprising: an array of memory cells, each memory cell including at least one transistor, the transistor including a source, a drain, a channel region between the source and drain, a control gate, an insulator between the control gate and the channel region, and a floating gate wherein die floating gate includes point defect trap sites that are carried by the insulator and electrically isolated from each other by intervening portions of the insulator and wherein the trap sites are carried in the insulator at an areal concentration that is between approximately 10 12 and approximately 10 15 trap sites per square centimeter; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 45
Dependent Claim
147 words
A memory device, comprising: an array of memory cells, each memory cell including at least one transistor, the transistor including a source, a drain, a channel region between the source and drain, a control gate, an insulator between the control gate and the channel region, and a floating gate wherein die floating gate includes point defect trap sites that are carried by the insulator and electrically isolated from each other by intervening portions of the insulator and wherein the trap sites are carried in the insulator at an areal concentration that is between approximately 10 12 and approximately 10 15 trap sites per square centimeter; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 46
Dependent Claim
19 words
The memory device of claim 34 wherein the trap sites are capable of capturing no more than one electron.
Claim 47
Dependent Claim
75 words
A memory cell including a transistor, the transistor including a source, a drain, a channel region between the source and the drain, a control gate and an insulator between the control gate and the channel region, and a floating gate wherein the floating gate includes point defect trap sites that are carried by the insulator at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator.
Claim 48
Dependent Claim
75 words
A memory cell including a transistor, the transistor including a source, a drain, a channel region between the source and the drain, a control gate and an insulator between the control gate and the channel region, and a floating gate wherein the floating gate includes point defect trap sites that are carried by the insulator at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator.
Claim 49
Dependent Claim
120 words
A memory device, comprising: an array of memory cells, at least one of the memory cells including a transistor, the transistor including a source, a drain, a channel region between the source and drain, a control gate, an insulator between the control gate and the channel region, and a floating gate wherein the floating gate includes point defect trap sites that are carried by the insulator and electrically isolated from each other by intervening portions of the insulator; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 50
Dependent Claim
120 words
A memory device, comprising: an array of memory cells, at least one of the memory cells including a transistor, the transistor including a source, a drain, a channel region between the source and drain, a control gate, an insulator between the control gate and the channel region, and a floating gate wherein the floating gate includes point defect trap sites that are carried by the insulator and electrically isolated from each other by intervening portions of the insulator; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 51
Dependent Claim
34 words
The memory device of claim 37 wherein the insulator of the at least one of the memory cells carries trap sites that arc electrically isolated from each other by intervening portions of the insulator.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-04-07 | 2006-10-07 | 2007-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-04-07 | 2010-10-07 | 2011-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-04-07 | 2014-10-07 | 2015-04-08 | $7700.00 | Window Closed / Lapsed |