US5754477A
Expired / Lapsed
US
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Differential flash memory cell and method for programming
Assignee: Micron Technology Inc
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Filing: 1997-01-29
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Granted: 1998-05-19
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Expires: 2017-01-29
Abstract
Abstract A flash memory cell. The flash memory cell includes first and second transistors. The first transistor has a control gate coupled to a word line, a drain coupled to a data line and a floating gate. The second transistor, similarly, includes a control gate coupled to the word line, a drain coupled to a second data line and a second floating gate. The first floating gate stores a state of the second transistor prior to programming of the flash memory cell. Further, the second floating gate stores a programmed state of the second transistor. A difference between the states of the first and second transistors represents the value of the data stored in the flash memory cell.
Inventors
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:43
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5642; G11C16/0408; G11C16/0441; G11C2211/00; G11C2211/56; G11C2211/561; G11C2211/5612; G11C2216/00; G11C2216/02; G11C2216/08
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
113 words
A flash memory cell, comprising: a first transistor with a control gate coupled to a word line, a drain coupled to a first data line, and a first floating gate; a second transistor with a control gate coupled to the word line, a drain coupled to a second data line, and a second floating gate; wherein the first floating gate stores a state of the second transistor prior to programming of the flash memory cell and the second floating gate stores a programmed state of the second transistor; and wherein a difference between the states of the first and second transistors represents the value of the data stored in the flash memory cell.
Claim 2
Dependent Claim
113 words
A flash memory cell, comprising: a first transistor with a control gate coupled to a word line, a drain coupled to a first data line, and a first floating gate; a second transistor with a control gate coupled to the word line, a drain coupled to a second data line, and a second floating gate; wherein the first floating gate stores a state of the second transistor prior to programming of the flash memory cell and the second floating gate stores a programmed state of the second transistor; and wherein a difference between the states of the first and second transistors represents the value of the data stored in the flash memory cell.
Claim 3
Dependent Claim
18 words
The flash memory cell of claim 1, wherein each floating gate comprises a number of crystals of silicon.
Claim 4
Dependent Claim
43 words
The flash memory cell of claim 1, wherein the memory cell further includes a load circuit that is coupleable to the first and second data lines to balance the state of the first and second transistors prior to programming the flash memory cell.
Claim 5
Independent Claim
92 words
A method of storing multiple bits of data in a flash memory cell, comprising the steps of: balancing a flash memory cell that includes a reference transistor and a storage transistor such that the transistors have substantially the same conductive state; and storing charge on the floating gate of the storage transistor so as to change the drain current of the storage transistor by a measurable amount, the amount of change in drain current corresponding to the value of the multiple bits of data to be stored in the flash memory cell.
Claim 6
Independent Claim
92 words
A method of storing multiple bits of data in a flash memory cell, comprising the steps of: balancing a flash memory cell that includes a reference transistor and a storage transistor such that the transistors have substantially the same conductive state; and storing charge on the floating gate of the storage transistor so as to change the drain current of the storage transistor by a measurable amount, the amount of change in drain current corresponding to the value of the multiple bits of data to be stored in the flash memory cell.
Claim 7
Dependent Claim
51 words
The method of claim 4, wherein the step of balancing the flash memory cell comprises the step of applying a load to first and second data lines of the flash memory cell so as to change the conductive state of one of the storage and reference transistors by hot electron injection.
Claim 8
Dependent Claim
53 words
The method of claim 4, wherein the step of storing charge on the floating gate of the storage transistor comprises the steps of: applying a first voltage to the data line of the storage transistor; and applying a second voltage, less than said first voltage, to the data line of the reference transistor.
Claim 9
Dependent Claim
93 words
A memory device, comprising: an array of flash memory cells, each cell including a reference transistor with a first floating gate and a storage transistor with a second floating gate; addressing circuitry coupled to the array for accessing a cell of the array; and a sense circuit that is coupled to the array to receive signals from the reference and storage transistors of an accessed memory cell so as to determine multiple bits of data stored in the memory cell based on the difference in drain current of the reference and storage transistors.
Claim 10
Dependent Claim
93 words
A memory device, comprising: an array of flash memory cells, each cell including a reference transistor with a first floating gate and a storage transistor with a second floating gate; addressing circuitry coupled to the array for accessing a cell of the array; and a sense circuit that is coupled to the array to receive signals from the reference and storage transistors of an accessed memory cell so as to determine multiple bits of data stored in the memory cell based on the difference in drain current of the reference and storage transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-18 | 2001-11-17 | 2002-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-18 | 2005-11-17 | 2006-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-18 | 2009-11-17 | 2010-05-19 | $7700.00 | Window Closed / Lapsed |