Nonvolatile semiconductor memory

Claim 2

A nonvolatile semiconductor memory device, comprising: a plurality of memory cells having transistors which are electrically and reversibly variable in threshold voltages; at least one pair of reference cells, provided for each predetermined number of memory cells, having transistors which have a construction in a direction of thickness roughly the same as that in a direction of thickness of the transistors constituting said memory cells; a driving means for writing and for also driving the at least one pair of reference cells when driving a selected memory cell and writing a first data in one reference cell and writing a second data inverted in phase from the first data in the other reference cell at the time of writing in the selected memory cell; a driving means for reading a data of the at least one pair of reference cells when reading a data of the selected memory cell; a reference current production means for combining a current:i 1 of the one reference cell corresponding to the first data and a current:i 0 of the other reference cell corresponding to the second data in the at least one pair of reference cells based on the following Equation (1) and preparing a k-multiple of a reference current:i re , or the reference current:i re i.sub.re =(m×i.sub.1 +n×i.sub.0)/k (1) where m, n, and k are positive numbers, and both of m and n are smaller than k; and a comparison means for determining a data stored in the selected memory cell by comparing the reference current: i re or the k-multiple of the reference current:i re produced by said production means with a current flowing in the selected memory cell or the k multiple of the current flowing in the selected memory cell.

Claim 3

A nonvolatile semiconductor memory device as set forth in claim 1, wherein said each predetermined number of memory cells and said at least one pair of reference cells are connected by an identical word line.

Claim 4

A nonvolatile semiconductor memory device as set forth in claim 1, wherein the transistors constituting said memory cells and the transistors constituting the reference cells are transistors having a floating gate which can store a charge, having an insulating film able to trap a charge, and having a strong dielectric film.

Claim 5

A nonvolatile semiconductor memory device as set forth in claim 1, wherein said comparison means comprises at least a differential amplifier as part of constituent elements of said comparison means and due to said reference current production means and said comparison means, a transistor constituting a part of said reference current production means acts also as a transistor of a part of the differential amplifier constituting said comparison means.

Claim 6

A nonvolatile semiconductor memory device as set forth in claim 4, comprising: a first current-to-voltage conversion transistor which converts to a voltage from a signal current of a joined interconnection at which output lines of said at least one pair of reference cells are joined and connected; a first transistor for the differential amplifier to which an output line of said first current-to-voltage conversion transistor is connected and which constitutes the transistor of the part of said differential amplifier; a second current-to-voltage conversion transistor which converts to a voltage from a signal current of an output line of said selected memory cell; and a second transistor for the differential amplifier to which an output line of said second current-to-voltage conversion transistor is connected and which constitutes the transistor of the part of said differential amplifier, wherein a mutual relationship exists among values obtained by dividing a channel width in said first current-to-voltage conversion transistor, said second current-to-voltage conversion transistor, said first transistor for the differential amplifier, and said second transistor for the differential amplifier by a channel length being set to a predetermined ratio.

Claim 7

A nonvolatile semiconductor memory device as set forth in claim 4, comprising: a first coefficient multiple conversion circuit for multiplying a signal current of an output line of said one reference cell by m or m/k; a second coefficient multiple conversion circuit for multiplying a signal current of an output line of said other reference cell by n or n/k; a joined interconnection circuit which joins an output line of said first coefficient multiple conversion circuit and an output line of said second coefficient multiple conversion circuit; a first current-to-voltage conversion transistor which converts to a voltage from a current flowing through the joined interconnection circuit; a first transistor for the differential amplifier to which an output line of said first current-to-voltage conversion transistor is connected and which constitutes the transistor of the part of said differential amplifier; a third coefficient multiple conversion circuit which multiplies a signal current of an output line of said selected memory cell by k or l; a second current-to-voltage conversion transistor which converts to a voltage from a signal current of an output line of the third coefficient multiple conversion circuit; and a second transistor for the differential amplifier to which an output line of said second current-to-voltage conversion transistor is connected and which constitutes the transistor of the part of said differential amplifier, wherein a mutual relationship exists among values obtained by dividing a channel width in a transistor of the first coefficient multiple conversion circuit, a transistor of the second coefficient multiple conversion circuit, a transistor of the third coefficient multiple conversion circuit, the first current-to-voltage conversion transistor, the second current-to-voltage conversion transistor, the first transistor for the differential amplifier, and the second transistor for the differential amplifier by a channel length being set to a predetermined ratio.

Claim 8

A nonvolatile semiconductor memory device as set forth in claim 4, comprising: a first coefficient multiple conversion circuit for multiplying a signal current of an output line of said one reference cell by m or m/k; a second coefficient multiple conversion circuit for multiplying a signal current of an output line of said other reference cell by n or n/k; a joined interconnection circuit which joins an output line of said first coefficient multiple conversion circuit and an output line of the second coefficient multiple conversion circuit; a first current-to-voltage conversion transistor which converts a current flowing through the joined interconnection circuit to a voltage; a first transistor for the differential amplifier to which an output line of said first current-to-voltage conversion transistor is connected and which constitutes the transistor of the part of said differential amplifier; a second current-to-voltage conversion transistor which converts a signal current of an output line of said selected memory cell to a voltage; and a second transistor for the differential amplifier to which an output line of said second current-to-voltage conversion transistor is connected and which constitutes the transistor of the part of said differential amplifier, wherein a mutual relationship exists among values obtained by dividing a channel width in a transistor of the first coefficient multiple conversion circuit, a transistor of the second coefficient multiple conversion circuit, the first current-to-voltage conversion transistor, the second current-to-voltage conversion transistor, the first transistor for the differential amplifier, and the second transistor for the differential amplifier by a channel length being set to a predetermined ratio.