US6521958B1
Expired / Lapsed
US
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MOSFET technology for programmable address decode and correction
Assignee: Nanya Technology Corp
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Filing: 1999-08-26
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Granted: 2003-02-18
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Expires: 2019-08-26
Abstract
Abstract Structures and methods for PLA capability on a DRAM chip according to a DRAM optimized process flow are provided by the present invention. These structures and methods include using MOSFET devices as re-programmable elements in memory address decode circuits in a DRAM integrated circuit. The structures and methods use the existing process sequence for MOSFET's in DRAM technology. An illustrative embodiment of the present invention includes a non-volatile, reprogrammable circuit switch. The circuit switch includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a source region, a drain region, a channel region between the source and drain regions, and a gate separated from the channel region by a gate oxide. The MOSFET is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region such that the channel region has a first voltage threshold region (Vt 1 ) and a second voltage threshold region (Vt 2 ), such that the programmed MOSFET operates at reduced drain source current.
Inventors
- 👤 Leonard Forbes
- 👤 Wendell P. Noble
- 👤 Eugene H. Cloud
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:55
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/785; G11C29/789; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4087; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; G11C8/00; G11C8/08; G11C8/10; H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356008; H10; H10B; H10B12/00; H10B12/50; H10D; H10D84/00; H10D84/90; H10D84/903
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
127 words
A circuit switch, comprising: a metal oxide semiconductor field effect transistor (MOSFET) in a substrate, the MOSFET having a source region, a drain region, a channel region between the source and drain regions, and a gate separated from the channel region by a gate oxide; a wordline coupled to the gate; a first transmission line coupled to the source region; a second transmission line coupled to the drain region; and wherein the MOSFET is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region has a first voltage threshold region (Vt 1 ) and a second voltage threshold region (Vt 2 ).
Claim 2
Dependent Claim
127 words
A circuit switch, comprising: a metal oxide semiconductor field effect transistor (MOSFET) in a substrate, the MOSFET having a source region, a drain region, a channel region between the source and drain regions, and a gate separated from the channel region by a gate oxide; a wordline coupled to the gate; a first transmission line coupled to the source region; a second transmission line coupled to the drain region; and wherein the MOSFET is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region has a first voltage threshold region (Vt 1 ) and a second voltage threshold region (Vt 2 ).
Claim 3
Dependent Claim
25 words
The circuit switch of claim 1 , wherein the first transmission line includes a source line and wherein the second transmission line includes a bitline.
Claim 4
Dependent Claim
30 words
The circuit switch of claim 2 wherein the source line is operatively coupled to the source region of the MOSFET and the bitline is operatively coupled to the drain region.
Claim 5
Dependent Claim
24 words
The circuit switch of claim 1 , wherein the charge trapped in the gate oxide adjacent the source region includes a trapped electron charge.
Claim 6
Dependent Claim
138 words
A circuit switch, comprising: a n-channel metal oxide semiconductor field effect transistor (NMOS) in a substrate, the NMOS having a source region, a drain region, a channel region between the source and region regions, and a gate separated from the channel region by a gate oxide; a wordline coupled to the gate; a source line operatively coupled to source region; a bitline operatively coupled to the drain region; and wherein the NMOS is a programmed NMOS having an electron charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region has a first voltage threshold region (Vt 1 ) and a second voltage threshold region (Vt 2 ), Vt 2 having a higher voltage threshold than Vt 1 .
Claim 7
Dependent Claim
138 words
A circuit switch, comprising: a n-channel metal oxide semiconductor field effect transistor (NMOS) in a substrate, the NMOS having a source region, a drain region, a channel region between the source and region regions, and a gate separated from the channel region by a gate oxide; a wordline coupled to the gate; a source line operatively coupled to source region; a bitline operatively coupled to the drain region; and wherein the NMOS is a programmed NMOS having an electron charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region has a first voltage threshold region (Vt 1 ) and a second voltage threshold region (Vt 2 ), Vt 2 having a higher voltage threshold than Vt 1 .
Claim 8
Dependent Claim
54 words
The circuit switch of claim 1 , wherein the second voltage threshold region (Vt 2 ) in the channel is adjacent the source region, the first voltage threshold region (Vt 1 ) in the channel is adjacent the drain region wherein the Vt 2 has a higher voltage threshold than the Vt 1 .
Claim 9
Dependent Claim
16 words
The circuit switch of claim 1 , wherein the programmed MOSFET includes a non-volatile, reprogrammable MOSFET.
Claim 10
Dependent Claim
153 words
A non-volatile, reprogrammable switch, comprising: a metal oxide semiconductor field effect transistor (MOSFET) in a substrate, the MOSFET having a source region, a drain region, a channel region between the source region and the drain region, and a gate separated from the channel region by a gate oxide; a wordline coupled to the gate; a first transmission line coupled to the source region; a second transmission line coupled to the drain region; and wherein the MOSFET is a programmed MOSFET having an electron charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region has a first voltage threshold region (Vt 1 ) adjacent to the drain region and a second voltage threshold region (Vt 2 ) adjacent to the source region, the Vt 2 having a greater voltage threshold than Vt 1 .
Claim 11
Dependent Claim
153 words
A non-volatile, reprogrammable switch, comprising: a metal oxide semiconductor field effect transistor (MOSFET) in a substrate, the MOSFET having a source region, a drain region, a channel region between the source region and the drain region, and a gate separated from the channel region by a gate oxide; a wordline coupled to the gate; a first transmission line coupled to the source region; a second transmission line coupled to the drain region; and wherein the MOSFET is a programmed MOSFET having an electron charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region has a first voltage threshold region (Vt 1 ) adjacent to the drain region and a second voltage threshold region (Vt 2 ) adjacent to the source region, the Vt 2 having a greater voltage threshold than Vt 1 .
Claim 12
Dependent Claim
182 words
A latch on a substrate, comprising: a pair of cross coupled inverters, wherein each inverter includes a first conduction type MOSFET and a second conduction type MOSFET, each MOSFET has a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate oxide; a first transmission line coupled to the gates of a first inverter in the cross coupled pair and to the drain regions of a second inverter in the cross coupled pair; a second transmission line coupled to the gates of a second inverter in the cross coupled pair and to the drain regions of a first inverter in the cross coupled pair; and wherein at least one of the MOSFETs is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region has a first voltage threshold region (Vt 1 ) and a second voltage threshold region (Vt 2 ).
Claim 13
Dependent Claim
182 words
A latch on a substrate, comprising: a pair of cross coupled inverters, wherein each inverter includes a first conduction type MOSFET and a second conduction type MOSFET, each MOSFET has a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate oxide; a first transmission line coupled to the gates of a first inverter in the cross coupled pair and to the drain regions of a second inverter in the cross coupled pair; a second transmission line coupled to the gates of a second inverter in the cross coupled pair and to the drain regions of a first inverter in the cross coupled pair; and wherein at least one of the MOSFETs is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region has a first voltage threshold region (Vt 1 ) and a second voltage threshold region (Vt 2 ).
Claim 14
Dependent Claim
31 words
The latch of claim 9 , wherein the first conduction type MOSFETs in each inverter include n-channel type MOSFETs (NMOS) and the second conduction type MOSFETs include p-channel type MOSFETs (PMOS).
Claim 15
Dependent Claim
41 words
The latch of claim 9 , wherein the source regions in the first conduction type MOSFETs are coupled to a first voltage potential, and wherein the drain regions in the second conduction type MOSFETs are coupled to a second voltage potential.
Claim 16
Dependent Claim
30 words
The latch of claim 9 , wherein the source of the at least one MOSFET is coupled to the source region of a MOSFET that is not a programmed MOSFET.
Claim 17
Dependent Claim
26 words
The latch of claim 9 , wherein the latch further includes an input line operatively coupled to the first transmission line and the second transmission line.
Claim 18
Dependent Claim
23 words
The latch of claim 9 , wherein the charge trapped in the gate oxide adjacent the source region includes a trapped electron charge.
Claim 19
Dependent Claim
71 words
The latch of claim 9 , wherein the second voltage threshold region (Vt 2 ) in the channel in the programmed MOSFET is adjacent to the source region of the programmed MOSFET, the first voltage threshold region (Vt 1 ) in the channel in the programmed MOSFET is adjacent the drain region of the programmed MOSFET, and wherein the Vt 2 has a higher voltage threshold than the Vt 1 .
Claim 20
Dependent Claim
226 words
A programmable decoder, comprising: an array of latches on a substrate, wherein each latch comprises: a pair of cross coupled inverters, wherein each inverter includes a first conduction type MOSFET and a second conduction type MOSFET, each MOSFET has a source region, a drain region, a channel region between the source and drain regions, and a gate separated from the channel region by a gate oxide; a number of first transmission lines coupled to the gates of the a first inverter in the cross coupled pair of inverters in the array of latches, and to the drain regions of a second inverter in the cross coupled pair of inverters in the array of latches; a number of second transmission lines coupled to the gates of the a second inverter in the cross coupled pair of inverters in the array of latches, and to the drain regions of a first inverter in the cross coupled pair of inverters in the array of latches; and wherein at least one latch includes a MOSFET which is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region has a first voltage threshold region (Vt 1 ) and a second voltage threshold region (Vt 2 ).
Claim 21
Dependent Claim
226 words
A programmable decoder, comprising: an array of latches on a substrate, wherein each latch comprises: a pair of cross coupled inverters, wherein each inverter includes a first conduction type MOSFET and a second conduction type MOSFET, each MOSFET has a source region, a drain region, a channel region between the source and drain regions, and a gate separated from the channel region by a gate oxide; a number of first transmission lines coupled to the gates of the a first inverter in the cross coupled pair of inverters in the array of latches, and to the drain regions of a second inverter in the cross coupled pair of inverters in the array of latches; a number of second transmission lines coupled to the gates of the a second inverter in the cross coupled pair of inverters in the array of latches, and to the drain regions of a first inverter in the cross coupled pair of inverters in the array of latches; and wherein at least one latch includes a MOSFET which is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region has a first voltage threshold region (Vt 1 ) and a second voltage threshold region (Vt 2 ).
Claim 22
Dependent Claim
35 words
The programmable decoder of claim 16 , wherein the number of first transmission lines include a number of address input lines and wherein the number of second transmission lines includes a number of output lines.
Claim 23
Dependent Claim
29 words
The programmable decoder of claim 16 , wherein the charge trapped in the gate oxide adjacent to the source region of the programmed MOSFET includes a trapped electron charge.
Claim 24
Dependent Claim
65 words
The programmable decoder of claim 16 , wherein the second voltage threshold region (Vt 2 ) in the channel of the programmed MOSFET is adjacent to the source region, the first voltage threshold region (Vt 1 ) in the channel of the programmed MOSFET is adjacent to the drain region, and wherein the Vt 2 has a higher voltage threshold than the Vt 1 .
Claim 25
Dependent Claim
16 words
The programmable decoder of claim 16 , wherein the programmed MOSFET includes a non-volatile, reprogrammable MOSFET.
Claim 26
Dependent Claim
255 words
An integrated circuit, comprising: an array of latches on a substrate, wherein each latch comprises: a pair of cross coupled inverters, wherein each inverter includes a first conduction type MOSFET and a second conduction type MOSFET, each MOSFET has a source region, a source region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate oxide; a number of first transmission lines coupled to the gates of the a first inverter in the cross coupled pair of inverters in the array of latches, and to the drain regions of a second inverter in the cross coupled pair of inverters in the array of latches; a number of second transmission lines coupled to the gates of the a second inverter in the cross coupled pair of inverters in the array of latches, and to the drain regions of a first inverter in the cross coupled pair of inverters in the array of latches; an address driver coupled to the number of first transmission lines; a number of row drivers and at least one redundant row driver coupled to the number of second transmission lines; and wherein at least one latch includes a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region has a first voltage threshold region (Vt 1 ) and a second voltage threshold region (Vt 2 ).
Claim 27
Dependent Claim
255 words
An integrated circuit, comprising: an array of latches on a substrate, wherein each latch comprises: a pair of cross coupled inverters, wherein each inverter includes a first conduction type MOSFET and a second conduction type MOSFET, each MOSFET has a source region, a source region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate oxide; a number of first transmission lines coupled to the gates of the a first inverter in the cross coupled pair of inverters in the array of latches, and to the drain regions of a second inverter in the cross coupled pair of inverters in the array of latches; a number of second transmission lines coupled to the gates of the a second inverter in the cross coupled pair of inverters in the array of latches, and to the drain regions of a first inverter in the cross coupled pair of inverters in the array of latches; an address driver coupled to the number of first transmission lines; a number of row drivers and at least one redundant row driver coupled to the number of second transmission lines; and wherein at least one latch includes a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region has a first voltage threshold region (Vt 1 ) and a second voltage threshold region (Vt 2 ).
Claim 28
Dependent Claim
32 words
The integrated circuit of claim 21 , wherein the first conduction type MOSFETs in each inverter include n-channel type MOSFETs (NMOS) and the second conduction type MOSFETs include p-channel type MOSFETs (PMOS).
Claim 29
Dependent Claim
42 words
The integrated circuit of claim 21 , wherein the source regions in the first conduction type MOSFETs are coupled to a first voltage potential, and wherein the source regions in the second conduction type MOSFETs are coupled to a second voltage potential.
Claim 30
Dependent Claim
31 words
The integrated circuit of claim 21 , wherein the source of the at least one MOSFET is coupled to the source region of a MOSFET that is not a programmed MOSFET.
Claim 31
Dependent Claim
32 words
The integrated circuit of claim 21 , wherein each latch in the array of latches further includes an input line operatively coupled to the first transmission line and the second transmission line.
Claim 32
Dependent Claim
90 words
The integrated circuit of claim 21 , wherein the second voltage threshold region (Vt 2 ) in the channel in the at least one programmed MOSFET is adjacent to the source region of the programmed MOSFET, the first voltage threshold region (Vt 1 ) in the channel in the at least one programmed MOSFET is adjacent to the drain of the programmed MOSFET, and wherein the Vt 2 has a higher voltage threshold than the Vt 1 and the first source/drain region of the programmed MOSFET is a source region.
Claim 33
Dependent Claim
35 words
The integrated circuit of claim 21 , wherein the number of first transmission lines include a number of address input lines, and wherein the number of second transmission lines include a number of output lines.
Claim 34
Dependent Claim
265 words
An electronic system, comprising: a memory; and a processor coupled to the memory, wherein the memory includes a programmable decoder, the programmable decoder comprising: an array of latches on a substrate, wherein each latch includes a pair of cross coupled inverters, wherein each inverter includes an n-channel MOSFET (NMOS) and a p-channel MOSFET (PMOS), each MOSFET has a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate oxide, and wherein the NMOS and PMOS of each inverter are coupled at the drain region; a number of address input lines coupled to the gates of a first inverter in the cross coupled pair of inverters in the array of latches, and to the drain region of a second inverter in the cross coupled pair of inverters in the array of latches; a number of output lines coupled to the gates of the a second inverter in the cross coupled pair of inverters in the array of latches, and to the drain region of a first inverter in the cross coupled pair of inverters in the array of latches; and wherein at least one of the MOSFETs in the array of latches is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region of the programmed MOSFET has a first voltage threshold region (Vt 1 ) and a second voltage threshold region (Vt 2 ).
Claim 35
Dependent Claim
265 words
An electronic system, comprising: a memory; and a processor coupled to the memory, wherein the memory includes a programmable decoder, the programmable decoder comprising: an array of latches on a substrate, wherein each latch includes a pair of cross coupled inverters, wherein each inverter includes an n-channel MOSFET (NMOS) and a p-channel MOSFET (PMOS), each MOSFET has a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate oxide, and wherein the NMOS and PMOS of each inverter are coupled at the drain region; a number of address input lines coupled to the gates of a first inverter in the cross coupled pair of inverters in the array of latches, and to the drain region of a second inverter in the cross coupled pair of inverters in the array of latches; a number of output lines coupled to the gates of the a second inverter in the cross coupled pair of inverters in the array of latches, and to the drain region of a first inverter in the cross coupled pair of inverters in the array of latches; and wherein at least one of the MOSFETs in the array of latches is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region and substantially no charge trapped in the gate oxide adjacent to the drain region such that the channel region of the programmed MOSFET has a first voltage threshold region (Vt 1 ) and a second voltage threshold region (Vt 2 ).
Claim 36
Dependent Claim
44 words
The electronic system of claim 28 , wherein the source regions in the PMOS transistors in each latch are coupled to a first voltage potential, and wherein the source regions in the NMOS transistors in each latch are coupled to a second voltage potential.
Claim 37
Dependent Claim
25 words
The electronic system of claim 28 , wherein memory coupled to the processor includes a memory coupled to the processor on a single semiconductor chip.
Claim 38
Dependent Claim
35 words
The electronic system of claim 28 , wherein each latch in the array of latches further includes an input line operatively coupled to the number of address lines and to the number of output lines.
Claim 39
Dependent Claim
79 words
The electronic system of claim 28 , wherein the second voltage threshold region (Vt 2 ) in the channel in the at least one programmed MOSFET is adjacent to the source region of the programmed MOSFET, the first voltage threshold region (Vt 1 ) in the channel in the at least one programmed MOSFET is adjacent to the drain region of the programmed MOSFET, and wherein the Vt 2 has a higher voltage threshold than the Vt 1 .
Claim 40
Dependent Claim
61 words
The electronic system of claim 28 , wherein the number of address input lines include a number of address input lines coupled to each latch in the array of latches from an address driver, and wherein the number of output lines include a number of output lines coupled to at least one row driver and at least one redundant row driver.
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