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US5801401A
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Flash memory with microcrystalline silicon carbide film floating gate
Assignee: Micron Technology Inc
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Filing: 1997-01-29
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Granted: 1998-09-01
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Expires: 2017-01-29
Abstract
Abstract A memory is described which has memory cells that store data using hot electron injection. The data is erased through electron tunneling. The memory cells are described as floating gate transistors wherein the floating gate is fabricated using a conductive layer of microcrystalline silicon carbide particles. The microcrystalline silicon carbide particles are in contact such that a charge stored on the floating gate is shared between the particles. The floating gate has a reduced electron affinity to allow for data erase operations using lower voltages.
Inventors
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:00
CPC Classifications
B; B82; B82Y; B82Y10/00; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D30/6891; H10D30/6893; H10D64/00; H10D64/60; H10D64/66; H10D64/667; Y; Y10; Y10S; Y10S438/00; Y10S438/931
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
42 words
An integrated circuit memory cell comprising: a transistor having a source, drain, control gate and a floating gate, the floating gate comprising a film of microcrystalline silicon carbide particles, the microcrystalline silicon carbide particles being in contact to form a conductive film.
Claim 2
Dependent Claim
42 words
An integrated circuit memory cell comprising: a transistor having a source, drain, control gate and a floating gate, the floating gate comprising a film of microcrystalline silicon carbide particles, the microcrystalline silicon carbide particles being in contact to form a conductive film.
Claim 3
Dependent Claim
36 words
The integrated circuit memory cell of claim 1 wherein the film of microcrystalline silicon carbide comprises a plurality of microscale silicon carbide particles each having a diameter in a range of about 30 to 100 Angstroms.
Claim 4
Dependent Claim
30 words
An integrated circuit memory cell comprising: a transistor having a source, drain, control gate and a floating gate, the floating gate comprising a conductive film of microcrystalline silicon carbide particles.
Claim 5
Dependent Claim
30 words
An integrated circuit memory cell comprising: a transistor having a source, drain, control gate and a floating gate, the floating gate comprising a conductive film of microcrystalline silicon carbide particles.
Claim 6
Dependent Claim
66 words
An integrated circuit field effect transistor comprising: a source region; a drain region; a conductive channel separating the source and drain regions; a floating gate comprising a conductive film of microcrystalline silicon carbide particles, the floating gate located adjacent the channel and separated therefrom by a first insulating layer; and a control gate located adjacent the floating gate and separated therefrom by a second insulating layer.
Claim 7
Dependent Claim
66 words
An integrated circuit field effect transistor comprising: a source region; a drain region; a conductive channel separating the source and drain regions; a floating gate comprising a conductive film of microcrystalline silicon carbide particles, the floating gate located adjacent the channel and separated therefrom by a first insulating layer; and a control gate located adjacent the floating gate and separated therefrom by a second insulating layer.
Claim 8
Dependent Claim
37 words
The integrated circuit field effect transistor of claim 4 wherein the film of microcrystalline silicon carbide comprises a plurality of microscale silicon carbide particles each having a diameter in a range of about 30 to 100 Angstroms.
Claim 9
Dependent Claim
20 words
The integrated circuit field effect transistor of claim 4 wherein the first and second insulating layers are comprised of oxide.
Claim 10
Dependent Claim
110 words
A memory device comprising: an array of memory cells, each of the memory cells comprising: a source region, a drain region coupled to a bit line, a conductive channel separating the source and drain regions, a floating gate comprising a conductive film of microcrystalline silicon carbide particles, the floating gate located adjacent the channel and separated therefrom by a first insulating layer, and a control gate located adjacent the floating gate and separated therefrom by a second insulating layer, the control gate is coupled to a word line; addressing circuitry for addressing the array of memory cells; and control circuitry for controlling read and write operations of the memory device.
Claim 11
Dependent Claim
110 words
A memory device comprising: an array of memory cells, each of the memory cells comprising: a source region, a drain region coupled to a bit line, a conductive channel separating the source and drain regions, a floating gate comprising a conductive film of microcrystalline silicon carbide particles, the floating gate located adjacent the channel and separated therefrom by a first insulating layer, and a control gate located adjacent the floating gate and separated therefrom by a second insulating layer, the control gate is coupled to a word line; addressing circuitry for addressing the array of memory cells; and control circuitry for controlling read and write operations of the memory device.
Claim 12
Dependent Claim
14 words
The memory device of claim 7 wherein the memory device is a flash memory.
Claim 13
Dependent Claim
25 words
The memory device of claim 7 wherein the microcrystalline silicon carbide particles each having a diameter in a range of about 30 to 100 Angstroms.
Claim 14
Independent Claim
65 words
A method of storing data in a flash memory device having an array of memory cells addressable by word and bit lines, comprising the steps of: increasing a voltage applied to a control gate of a memory cell, the memory cell including a floating gate comprising a conductive film of microcrystalline silicon carbide particles; and trapping electrons on the floating gate by hot electron injection.
Claim 15
Independent Claim
65 words
A method of storing data in a flash memory device having an array of memory cells addressable by word and bit lines, comprising the steps of: increasing a voltage applied to a control gate of a memory cell, the memory cell including a floating gate comprising a conductive film of microcrystalline silicon carbide particles; and trapping electrons on the floating gate by hot electron injection.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-08-31 | 2002-03-02 | 2002-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-31 | 2006-03-02 | 2006-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-31 | 2010-03-02 | 2010-09-01 | $7700.00 | Window Closed / Lapsed |