US5959896A — Multi-state flash memory cell and method for prog…

Claim 1

Independent Claim 87 words

A flash memory cell, comprising: a transistor with a control gate coupled to a word line, a drain region coupled to a data line, and a floating gate that stores a value that represents a number of bits of data; and wherein the floating gate comprises a number of conductive elements implanted at a position in a gate oxide of the transistor, wherein the size and location of the conductive elements are selected such that each conductive element traps at most one electron by hot electron injection.

Claim 2

Dependent Claim 87 words

A flash memory cell, comprising: a transistor with a control gate coupled to a word line, a drain region coupled to a data line, and a floating gate that stores a value that represents a number of bits of data; and wherein the floating gate comprises a number of conductive elements implanted at a position in a gate oxide of the transistor, wherein the size and location of the conductive elements are selected such that each conductive element traps at most one electron by hot electron injection.

Claim 3

Dependent Claim 32 words

The flash memory cell of claim 1, wherein the floating gate is disposed at a distance of approximately 60 to 100 angstroms from a surface of a semiconductor layer of the transistor.

Claim 4

Dependent Claim 102 words

A transistor, comprising: a layer of semiconductor material; first and second source/drain regions implanted in the semiconductor material; a gate oxide disposed outwardly from the layer of semiconductor material; a control gate disposed outwardly from the gate oxide; and a floating gate including a number of conductive elements that are implanted in the gate oxide at a distance from a surface of the semiconductor material, wherein the conductive elements have a size and are disposed at a distance from the surface of the layer of semiconductor material such that the conductive elements each trap at most one electron by hot electron injection.

Claim 5

Dependent Claim 102 words

A transistor, comprising: a layer of semiconductor material; first and second source/drain regions implanted in the semiconductor material; a gate oxide disposed outwardly from the layer of semiconductor material; a control gate disposed outwardly from the gate oxide; and a floating gate including a number of conductive elements that are implanted in the gate oxide at a distance from a surface of the semiconductor material, wherein the conductive elements have a size and are disposed at a distance from the surface of the layer of semiconductor material such that the conductive elements each trap at most one electron by hot electron injection.

Claim 6

Dependent Claim 19 words

The transistor of claim 3, wherein the conductive elements comprise crystals of semiconductor material implanted in the gate oxide.

Claim 7

Dependent Claim 27 words

The transistor of claim 4, wherein the crystals are disposed at a distance of 60 to 100 angstroms from the surface of the layer of semiconductor material.

Claim 8

Dependent Claim 109 words

A memory device, comprising: a first array of flash memory cells with implanted floating gates; a second array of flash memory cells with implanted floating gates, each cell storing the state of an associated cell of the first array for a time prior to storing data in the associated cell of the first array; a word line decoder and a data line decoder coupled to the first and second arrays for accessing associated cells of the first and second arrays; and a read circuit coupled to the first and second arrays that compares the values of associated cells of the first and second arrays to produce an output signal.

Claim 9

Dependent Claim 109 words

A memory device, comprising: a first array of flash memory cells with implanted floating gates; a second array of flash memory cells with implanted floating gates, each cell storing the state of an associated cell of the first array for a time prior to storing data in the associated cell of the first array; a word line decoder and a data line decoder coupled to the first and second arrays for accessing associated cells of the first and second arrays; and a read circuit coupled to the first and second arrays that compares the values of associated cells of the first and second arrays to produce an output signal.

Claim 10

Dependent Claim 31 words

The memory device of claim 6, wherein the implanted floating gates each comprise a number of crystals disposed in a gate oxide so as to trap electrons by hot electron injection.

Claim 11

Dependent Claim 143 words

A memory device comprising: a first array of flash memory cells with implanted floating gates a second array of flash memory cells with implanted floating gates, each cell storing the state of an associated cell of the first array for a time prior to storing data in the associated cell of the first array; a word line decoder and a data line decoder coupled to the first and second arrays for accessing associated cells of the first and second arrays; a read circuit coupled to the first and second arrays that compares the values of associated cells of the first and second arrays to produce an output signal; and wherein each memory cell includes a field-effect transistor formed on a semiconductor layer, and each floating gate comprises nano-crystals that are disposed at a distance of 60 to 100 angstroms from the semiconductor layer.

Claim 12

Dependent Claim 143 words

A memory device comprising: a first array of flash memory cells with implanted floating gates a second array of flash memory cells with implanted floating gates, each cell storing the state of an associated cell of the first array for a time prior to storing data in the associated cell of the first array; a word line decoder and a data line decoder coupled to the first and second arrays for accessing associated cells of the first and second arrays; a read circuit coupled to the first and second arrays that compares the values of associated cells of the first and second arrays to produce an output signal; and wherein each memory cell includes a field-effect transistor formed on a semiconductor layer, and each floating gate comprises nano-crystals that are disposed at a distance of 60 to 100 angstroms from the semiconductor layer.

Claim 13

Dependent Claim 45 words

The memory device of claim 8, wherein the size of the nano-crystals is chosen such that a single electron trapped by the nano-crystal changes the voltage of the nano-crystal sufficiently so that the nano-crystal repels other electrons that approach the nano-crystal during a write operation.

Claim 14

Dependent Claim 141 words

A memory device, comprising: a first array of flash memory cells with implanted floating gates; a second array of flash memory cells with implanted floating gates, each cell storing the state of an associated cell of the first array for a time prior to storing data in the associated cell of the first array; a word line decoder and a data line decoder coupled to the first and second arrays for accessing associated cells of the first and second arrays; a read circuit coupled to the first and second arrays that compares the values of associated cells of the first and second arrays to produce an output signal; wherein the implanted floating gates each comprise a number of crystals disposed in a gate oxide so as to trap electrons by hot electron injection and wherein the crystals comprise a semiconductor material.

Claim 15

Dependent Claim 141 words

A memory device, comprising: a first array of flash memory cells with implanted floating gates; a second array of flash memory cells with implanted floating gates, each cell storing the state of an associated cell of the first array for a time prior to storing data in the associated cell of the first array; a word line decoder and a data line decoder coupled to the first and second arrays for accessing associated cells of the first and second arrays; a read circuit coupled to the first and second arrays that compares the values of associated cells of the first and second arrays to produce an output signal; wherein the implanted floating gates each comprise a number of crystals disposed in a gate oxide so as to trap electrons by hot electron injection and wherein the crystals comprise a semiconductor material.

Claim 16

Independent Claim 94 words

A method of storing data in a flash memory device having an array of memory cells addressable by word and data lines, comprising: applying a voltage to a control gate of a selected memory cell; trapping electrons on conductive elements implanted in a gate oxide of the selected memory cell by hot electron injection; monitoring step changes in current of the selected memory cell; and changing the voltage on the control gate when the current has changed by a number of steps corresponding to a desired value to be stored in the memory cell.

Claim 17

Independent Claim 94 words

A method of storing data in a flash memory device having an array of memory cells addressable by word and data lines, comprising: applying a voltage to a control gate of a selected memory cell; trapping electrons on conductive elements implanted in a gate oxide of the selected memory cell by hot electron injection; monitoring step changes in current of the selected memory cell; and changing the voltage on the control gate when the current has changed by a number of steps corresponding to a desired value to be stored in the memory cell.

Claim 18

Dependent Claim 19 words

The method of claim 11, and further comprising applying a voltage to a drain of the selected memory cell.

Claim 19

Independent Claim 82 words

A method of storing data in a memory device, the method comprising: trapping an electron on a floating gate of a memory cell, the floating gate comprising a number implanted, conductive elements; monitoring step changes in the drain current of a transistor in the memory cell; and repeating the trapping and monitoring steps until the drain current has changed by an amount that is associated with the value of the data to be stored on the floating gate of the memory cell.

Claim 20

Independent Claim 82 words

A method of storing data in a memory device, the method comprising: trapping an electron on a floating gate of a memory cell, the floating gate comprising a number implanted, conductive elements; monitoring step changes in the drain current of a transistor in the memory cell; and repeating the trapping and monitoring steps until the drain current has changed by an amount that is associated with the value of the data to be stored on the floating gate of the memory cell.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-09-27	2003-03-29	2003-09-28	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-09-27	2007-03-29	2007-09-28	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-09-27	2011-03-29	2011-09-28	$7700.00	Window Closed / Lapsed

Multi-state flash memory cell and method for programming single electron differences

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