EP0448118A2
Expired / Lapsed
EP
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Differential cell-type EPROM incorporating stress test circuit
Assignee: Toshiba Corp
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Filing: 1991-03-22
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Granted: —
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Expires: 2011-03-22
Abstract
Abstract The differential cell-type non-volatile semiconductor device having first and second memory cell arrays (MCA1, MCA2). Two cell transistors (MC, MC ) of corresponding addresses in the first and second memory cell arrays (MCA1, MCA2) are uses to constitute a single memory cell. Each of writing transistors (WT1, WT2) for wiring data in the cell transistors (MC, MC ) is provided to the first and second memory cell arrays (MCA1, MCA2). Complementary data are written in the two cell transistors (MC, MC ) selected in the first and second memory cell arrays (MCA1, MCA2). Readout potentials from the two cell transistors (MC, MC ) are amplified by a differential amplifier (DFA), thereby reading out stored data. The memory device has a stress test control circuit (10, 21) for controlling, in a stress test mode, writing transistors (WT1, WT2) such that they are all simultaneously turned on/off.
Inventors
- 👤 Shigeru C/O Intellectual Property Div. Atsumi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 13:30
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/50; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; G11C16/06; G11C16/08; G11C16/34
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
228 words
A differential cell-type non-volatile semiconductor memory device, characterized by comprising: a plurality of memory cell arrays (MCAl, MCA2) having matrices of memory cells (MCll to MCij, MCll to MCij ); row selecting means (11, 13) for selecting memory cells (MC) connected to corresponding rows of said plurality of memory cell arrays (MCAl, MCA2); column selecting means (12, 14) for selecting memory cells (MC) connected to corresponding columns of said plurality of memory cell arrays (MCAl, MCA2); differential amplifier means (DFA) for differentially amplifying data read out from said memory cells (MC) of corresponding addresses of said plurality of memory cell arrays (MCAl, MCA2) that are selected from said plurality of memory cell arrays (MCA1, MCA2) by said row selecting means (11, 13) and said column selecting means (12, 14); readout means for reading out data in accordance with an output from said differential amplifier means (DFA); write means (15, 16, 17, 18, 19), having a plurality of corresponding write transistors (WT1, WT2) for writing data in memory cells (MC) of said plurality of memory cell arrays (MCAl, MCA2), for writing complementary data in memory cells (MC) of corresponding addresses that are selected from said plurality of memory cell arrays (MCAl, MCA2); and stress test control means (21) for controlling, in a stress test mode, said plurality of writing transistors (WT1, WT2) so as to be simultaneously turned on/off.
Claim 2
Dependent Claim
35 words
A device according to claim 1, characterized in that said memory cells (MC) of said plurality of memory cell arrays (MCA1, MCA2) respectively include cell transistors each having a floating gate and a control gate.
Claim 3
Dependent Claim
43 words
A device according to claim 1, characterized in that said row selecting means includes a row address buffer circuit (13) for detecting a row address signal and a row decoder (11) for decoding an output signal from said row address buffer circuit (13).
Claim 4
Dependent Claim
52 words
A device according to claim 3, characterized in that in the stress test mode, said row decoder avoids to select all the rows of said plurality memory cell arrays (MCA1, MCA2) based on the control by the stress test signal (STS1, STS2) regardless of the level of the row address signal (Ai).
Claim 5
Dependent Claim
44 words
A device according to claim 1, characterized in that said column selecting means includes a column address buffer circuit (14) for detecting a column address signal (Aj) and a column decoder (12) for decoding an output signal from said column address buffer circuit (14).
Claim 6
Dependent Claim
54 words
A device according to claim 5, characterized in that in the stress test mode, said column address buffer circuit (14) avoids to select all the outputs (CD1 to CDj) from said column decoder (12) based on control by the stress test signal (STS1, STS2) regardless of the level of the column address signal (Aj).
Claim 7
Dependent Claim
50 words
A device according to claim 1, characterized in that said differential amplifier means includes a differential amplifier (DFA) having first and second input nodes, and first and second loads (L1, L2) respectively connected between said first and second input nodes of said differential amplifier (DFA) and a power source (Vcc).
Claim 8
Dependent Claim
181 words
A device according to claim 1, characterized in that said write means includes: first voltage transforming means (15) for transforming a power source voltage (Vcc) level signal to a high-potential power source (Vpp) level signal and turning on/off one (WT1) of said write transistors (WT1, WT2); second voltage transforming means (16) for transforming the power source voltage (Vcc) level signal to the high-potential power source (Vpp) level signal and turning on another one (WT2) of said write transistors (WT1, WT2); first logic means (17, 18) for supplying, in a write enable state, a write data signal (Din) to said first voltage transforming means (15); and second logic means (10, 20, 19), controlled by an output signal from said stress test control means (21), for supplying, in the write enable state and an ordinary write mode, an inverted signal of the write data signal (Din) to said second voltage transforming means (16), and, in a write enable state and the stress test mode, a signal of the same phase as the write data signal (Din) to said second voltage transforming means (16).
Claim 9
Dependent Claim
39 words
A device according to claim 1, characterized in that said stress test control means (10, 21) performs control such that said plurality of write transistors (WT1, WT2) are simultaneously turned on/off in accordance with the write data signal (Din).
Claim 10
Dependent Claim
24 words
A device according to claim 1, characterized in that said stress test control means (10, 21) operates based on an external three-value control voltage.
Claim 11
Dependent Claim
29 words
A device according to claim 10, characterized in that said stress test control means (10, 21) is controlled by an output from a three-value control circuit (24 to 29).
References Cited (Backward Citations)
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