US5943262A
Expired / Lapsed
US
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Non-volatile memory device and method for operating and fabricating the same
Assignee: Samsung Electronics Co Ltd
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Filing: 1998-10-28
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Granted: 1999-08-24
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Expires: 2018-10-28
Abstract
Abstract A non-volatile memory device includes a plurality of bit lines arranged in parallel at predetermined intervals, a plurality of word lines arranged perpendicularly to the bit lines and at predetermined intervals, a plurality of unit cells having a stacked gate structure comprising a floating gate and a control gate formed in regions where the bit lines and word lines perpendicularly intersect, a plurality of source lines parallel to the bit lines for connecting source active regions of cells to one another, the source active regions being shared by two symmetrical cells connected to an identical bit line through different bit line contacts, and source select transistors formed in overlap regions between source lines and word lines, for dividing the source active regions. For programming a cell, a cell current is generated by applying a positive voltage to a bit line and a word line of the selected cell and a reference voltage lower than the bit line voltage to a source line, and a voltage lower than the reference voltage is applied to a word line of an unselected cell sharing the source active region with the selected cell. Therefore, the limitations of overerasure can be avoided in a device which occupies the same cell area as that of conventional cell arrays.
Inventors
- 👤 Jeong-Hyuk Choi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:28
CPC Classifications
H; H10; H10B; H10B69/00; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; H10B41/00; H10B41/10; H10B41/40; H10B41/42; H10B41/43; H10B41/44
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
150 words
A non-volatile memory device comprising: a plurality of bit lines arranged in parallel at predetermined intervals; a plurality of word lines arranged perpendicularly to the bit lines and at predetermined intervals; a plurality of unit cells having a stacked gate structure including a floating gate a control gate formed in regions where the bit lines and word lines perpendicularly intersect; a plurality of source lines parallel to the bit lines, for connecting source active regions of cells; each source active region shared by two symmetrical cells connected to a common bit line; and a plurality of source select transistors formed in overlap regions between the source lines and the word lines; wherein the source select transistors have a single-layer gate structure including a gate insulating layer under the single-layer gate having a thickness of at least as thick as a gate insulating layer under the floating gate of the cell.
Claim 2
Dependent Claim
150 words
A non-volatile memory device comprising: a plurality of bit lines arranged in parallel at predetermined intervals; a plurality of word lines arranged perpendicularly to the bit lines and at predetermined intervals; a plurality of unit cells having a stacked gate structure including a floating gate a control gate formed in regions where the bit lines and word lines perpendicularly intersect; a plurality of source lines parallel to the bit lines, for connecting source active regions of cells; each source active region shared by two symmetrical cells connected to a common bit line; and a plurality of source select transistors formed in overlap regions between the source lines and the word lines; wherein the source select transistors have a single-layer gate structure including a gate insulating layer under the single-layer gate having a thickness of at least as thick as a gate insulating layer under the floating gate of the cell.
Claim 3
Dependent Claim
27 words
The non-volatile memory device of claim 1, wherein the active width of the source select transistor is approximately equal to or larger than that of the cell.
Claim 4
Dependent Claim
44 words
The non-volatile memory device of claim 1, further comprising first source/drain junctions aligned to the single-layer gate of the source select transistor and second source/drain junctions aligned to the stacked gate of the cell; the first and second source/drain junctions being different in structure.
Claim 5
Dependent Claim
45 words
The non-volatile memory device of claim 3, wherein the second source/drain junctions comprise one of a single diffusion (SD) junction and a double diffusion (DD) junction, and wherein the first source/drain junctions comprise one of an SD junction and a lightly doped drain (LDD) junction.
Claim 6
Dependent Claim
34 words
The non-volatile memory device of claim 3, wherein at least one of the first source/drain junctions has the same structure as that of source/drain junctions in a peripheral circuit transistor for driving the cell.
Claim 7
Dependent Claim
37 words
The non-volatile memory device of claim 1, wherein the source active region is divided into units of less than the number of cells in a word line direction and more than the number of input/output (I/O) terminals.
Claim 8
Independent Claim
200 words
A method of operating a non-volatile memory device having a plurality of bit lines arranged in parallel at predetermined intervals, a plurality of word lines arranged perpendicularly to the bit lines and at predetermined intervals, a plurality of unit cells having a stacked gate structure including a floating gate and a control gate formed in regions where the bit lines and word lines perpendicularly intersect, a plurality of source lines parallel to the bit lines for connecting source active regions of cells to one another, source active regions shared by two symmetrical cells being connected to a common bit line, and a plurality of source select transistors formed in overlap regions between the source lines and word lines, said method comprising: generating a cell current by applying a positive voltage to the corresponding bit line and the corresponding word line of a selected cell and applying a reference voltage lower than the bit line voltage to the corresponding source line, during programming of the selected cell for injecting electrons onto the floating gate thereof; and applying a voltage lower than the reference voltage to a word line of an unselected cell sharing the source active region with the selected cell.
Claim 9
Independent Claim
200 words
A method of operating a non-volatile memory device having a plurality of bit lines arranged in parallel at predetermined intervals, a plurality of word lines arranged perpendicularly to the bit lines and at predetermined intervals, a plurality of unit cells having a stacked gate structure including a floating gate and a control gate formed in regions where the bit lines and word lines perpendicularly intersect, a plurality of source lines parallel to the bit lines for connecting source active regions of cells to one another, source active regions shared by two symmetrical cells being connected to a common bit line, and a plurality of source select transistors formed in overlap regions between the source lines and word lines, said method comprising: generating a cell current by applying a positive voltage to the corresponding bit line and the corresponding word line of a selected cell and applying a reference voltage lower than the bit line voltage to the corresponding source line, during programming of the selected cell for injecting electrons onto the floating gate thereof; and applying a voltage lower than the reference voltage to a word line of an unselected cell sharing the source active region with the selected cell.
Claim 10
Dependent Claim
30 words
The method of claim 7, wherein the reference voltage is one of 0 V and a ground voltage and the voltage lower than the reference voltage is a negative voltage.
Claim 11
Dependent Claim
32 words
The method of claim 7, wherein a voltage higher than the threshold voltage of the source select transistor is applied to the word line of the selected cell during the programming operation.
Claim 12
Dependent Claim
18 words
The method of claim 7, further comprising the step of precharging the source line during the programming operation.
Claim 13
Dependent Claim
67 words
The method of claim 7, further comprising the step of performing a post programming operation for injecting fewer electrons onto the floating gate of the cell than those for the programming operation, wherein a negative voltage lower than a voltage on the word line of the unselected cell is applied to the word line of the unselected cell sharing the source active region with the selected cell.
Claim 14
Dependent Claim
33 words
The method of claim 11, wherein a voltage higher than the threshold voltage of the source select transistor is applied to the word line of the selected cell during the post programming operation.
Claim 15
Dependent Claim
19 words
The method of claim 11, further comprising the step of precharging the source line during the post programming operation.
Claim 16
Dependent Claim
22 words
The method of claim 7, wherein the initial threshold voltage of the source select transistor is lower than that of the cell.
Claim 17
Independent Claim
186 words
A method of operating a non-volatile memory device having a plurality of bit lines arranged in parallel at predetermined intervals, a plurality of word lines arranged perpendicularly to the bit lines and at predetermined intervals, a plurality of unit cells having a stacked gate structure including a floating gate and a control gate formed in regions where the bit lines and word lines perpendicularly intersect, a plurality of source lines parallel to the bit lines, for connecting source active regions of cells to one another, source active regions shared by two symmetrical cells being connected to a common bit line, and a plurality source select transistors formed in overlap regions between the source lines and word lines, the method comprising: applying a positive voltage to the corresponding bit line and the corresponding word line of a selected cell and applying a reference voltage lower than the bit line voltage to the corresponding source line during reading of the selected cell; and applying a voltage lower than the reference voltage to a word line of an unselected cell sharing the source active region with the selected cell.
Claim 18
Independent Claim
186 words
A method of operating a non-volatile memory device having a plurality of bit lines arranged in parallel at predetermined intervals, a plurality of word lines arranged perpendicularly to the bit lines and at predetermined intervals, a plurality of unit cells having a stacked gate structure including a floating gate and a control gate formed in regions where the bit lines and word lines perpendicularly intersect, a plurality of source lines parallel to the bit lines, for connecting source active regions of cells to one another, source active regions shared by two symmetrical cells being connected to a common bit line, and a plurality source select transistors formed in overlap regions between the source lines and word lines, the method comprising: applying a positive voltage to the corresponding bit line and the corresponding word line of a selected cell and applying a reference voltage lower than the bit line voltage to the corresponding source line during reading of the selected cell; and applying a voltage lower than the reference voltage to a word line of an unselected cell sharing the source active region with the selected cell.
Claim 19
Dependent Claim
30 words
The method of claim 15, wherein the reference voltage is one of 0 V and a ground voltage and the voltage lower than the reference voltage is a negative voltage.
Claim 20
Dependent Claim
32 words
The method of claim 15, wherein a voltage higher than the threshold voltage of the source select transistor is applied to the word line of the selected cell during the reading operation.
References Cited (Backward Citations)
US4698787A
Cited
US4888734A
Cited
US5596523A
Cited
US5638327A
Cited
US5491657A
Cited
US5877524A
Cited
US5812454A
Cited
US5790456A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-23 | 2003-02-22 | 2003-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-23 | 2007-02-22 | 2007-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-23 | 2011-02-22 | 2011-08-24 | $7700.00 | Window Closed / Lapsed |