Method for bulk (or byte) charging and discharging an array of flash EEPROM memory cells

Claim 1

A method for bulk (or byte) charging an array of flash EEPROM memory cells, said memory cells being formed on a substrate to define columns and rows, where the substrate includes a common source line extending along at least one of the rows, common substrate line, and a plurality of bit lines extending along respective columns, where each memory cell includes an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines, said method comprising the bulk (or byte) charging steps of: applying a negative voltage to the substrate of the array; applying simultaneously a reference voltage of zero volts to drain regions of selected memory cells in the array that are to be programmed; and applying simultaneously the same reference voltage of zero volts to control gates of the selected memory cells, said source regions being allowed to float.

Claim 2

A method for bulk (or byte) charging an array of flash EEPROM memory cells, said memory cells being formed on a substrate to define columns and rows, where the substrate includes a common source line extending along at least one of the rows, common substrate line, and a plurality of bit lines extending along respective columns, where each memory cell includes an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines, said method comprising the bulk (or byte) charging steps of: applying a negative voltage to the substrate of the array; applying simultaneously a reference voltage of zero volts to drain regions of selected memory cells in the array that are to be programmed; and applying simultaneously the same reference voltage of zero volts to control gates of the selected memory cells, said source regions being allowed to float.

Claim 11

A method for bulk (or byte) charging and source-side erasing an array of flash EEPROM memory cells, said memory cells being formed on a substrate to define columns and rows, where the substrate includes a common source line extending along at least one of the rows, a common substrate line, and a plurality of bit lines extending along respective columns, where each memory cell includes an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines, said method comprising the bulk (or byte) charging steps of: applying a first negative voltage to the substrate of the array; applying simultaneously a reference voltage of zero volts to drain regions of selected memory cells in the array that are to be programmed; applying simultaneously the same reference voltage of zero volts to control gates of the selected memory cells; said method further including the source-side erasing steps of applying zero volts to the substrate of the array; applying a positive voltage to the source regions of the array; and applying a second negative voltage to the control gates, said drain regions being allowed to float during erasure.

Claim 12

A method for bulk (or byte) charging and source-side erasing an array of flash EEPROM memory cells, said memory cells being formed on a substrate to define columns and rows, where the substrate includes a common source line extending along at least one of the rows, a common substrate line, and a plurality of bit lines extending along respective columns, where each memory cell includes an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines, said method comprising the bulk (or byte) charging steps of: applying a first negative voltage to the substrate of the array; applying simultaneously a reference voltage of zero volts to drain regions of selected memory cells in the array that are to be programmed; applying simultaneously the same reference voltage of zero volts to control gates of the selected memory cells; said method further including the source-side erasing steps of applying zero volts to the substrate of the array; applying a positive voltage to the source regions of the array; and applying a second negative voltage to the control gates, said drain regions being allowed to float during erasure.

Claim 21

A method for bulk (or byte) charging and flash erasing an array of flash EEPROM memory cells, said memory cells being formed on a substrate to define columns and rows, where the substrate includes a common source line extending along at least one of the rows, a common substrate line, and a plurality of bit lines extending along respective columns, where each memory cell includes an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines, said method comprising the bulk (or byte) charging steps of: applying a negative voltage to the substrate of the array; applying simultaneously a reference voltage of zero volts to drain regions of selected memory cells in the array that are to be programmed; applying simultaneously the same reference voltage of zero volts to control gates of the selected memory cells; said method further including the flash erasing steps of applying a positive voltage the same magnitude as voltage on said substrate during flash programming to the drain regions of the array; and applying the zero volts the same as that of said drain region during flash programming operations to the control gate and substrates of the array, said source regions being allowed to float during erasure.

Claim 22

A method for bulk (or byte) charging and flash erasing an array of flash EEPROM memory cells, said memory cells being formed on a substrate to define columns and rows, where the substrate includes a common source line extending along at least one of the rows, a common substrate line, and a plurality of bit lines extending along respective columns, where each memory cell includes an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines, said method comprising the bulk (or byte) charging steps of: applying a negative voltage to the substrate of the array; applying simultaneously a reference voltage of zero volts to drain regions of selected memory cells in the array that are to be programmed; applying simultaneously the same reference voltage of zero volts to control gates of the selected memory cells; said method further including the flash erasing steps of applying a positive voltage the same magnitude as voltage on said substrate during flash programming to the drain regions of the array; and applying the zero volts the same as that of said drain region during flash programming operations to the control gate and substrates of the array, said source regions being allowed to float during erasure.

Claim 24

A method for bulk (or byte) charging an array of flash EEPROM memory cells, said memory cells being formed on a substrate to define columns and rows, where the substrate includes common source line extending along at least one of the rows, a common substrate line, and a plurality of bit lines extending along respective columns, where each memory cell includes an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines, said method comprising the bulk (or byte) charging steps of: applying a reference voltage of zero volts to the substrate of the array; applying simultaneously a positive voltage to drain regions of selected memory cells in the array that are to be programmed; and applying simultaneously the same positive voltage to control gates of the selected memory cells, said source regions being allowed to float.

Claim 25

A method for bulk (or byte) charging an array of flash EEPROM memory cells, said memory cells being formed on a substrate to define columns and rows, where the substrate includes common source line extending along at least one of the rows, a common substrate line, and a plurality of bit lines extending along respective columns, where each memory cell includes an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines, said method comprising the bulk (or byte) charging steps of: applying a reference voltage of zero volts to the substrate of the array; applying simultaneously a positive voltage to drain regions of selected memory cells in the array that are to be programmed; and applying simultaneously the same positive voltage to control gates of the selected memory cells, said source regions being allowed to float.

Claim 26

A method for bulk (or byte) charging an array of flash EEPROM memory cells, said memory cells being formed on a substrate to define columns and rows, where the substrate includes common source line extending along at least one of the rows, a common substrate line, and a plurality of bit lines extending along respective columns, where each memory cell includes an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines, said method comprising the bulk (or byte) charging steps of: applying a reference voltage of zero volts to the substrate of the array; applying simultaneously a positive voltage to source regions of selected memory cells in the array that are to be programmed; and applying simultaneously the same positive voltage to control gates of the selected memory cells, said drain regions being allowed to float.

Claim 27

A method for bulk (or byte) charging an array of flash EEPROM memory cells, said memory cells being formed on a substrate to define columns and rows, where the substrate includes common source line extending along at least one of the rows, a common substrate line, and a plurality of bit lines extending along respective columns, where each memory cell includes an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines, said method comprising the bulk (or byte) charging steps of: applying a reference voltage of zero volts to the substrate of the array; applying simultaneously a positive voltage to source regions of selected memory cells in the array that are to be programmed; and applying simultaneously the same positive voltage to control gates of the selected memory cells, said drain regions being allowed to float.

Claim 28

A method for bulk (or byte) discharging an array of flash EEPROM memory cells, said memory cells being formed on a substrate to define columns and rows, where the substrate includes a common source line extending along at least one of the rows, a common substrate line, and a plurality of bit lines extending along respective columns, where each memory cell includes an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines, said method comprising the bulk (or byte) discharging steps of: applying a low negative voltage to the substrate of the array; applying simultaneously an intermediate positive voltage to drain regions of selected memory cells in the array that are to be erased; and applying simultaneously a reference voltage of zero volts to control gates of the selected memory cells, said source regions being allowed to float.

Claim 29

A method for bulk (or byte) discharging an array of flash EEPROM memory cells, said memory cells being formed on a substrate to define columns and rows, where the substrate includes a common source line extending along at least one of the rows, a common substrate line, and a plurality of bit lines extending along respective columns, where each memory cell includes an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines, said method comprising the bulk (or byte) discharging steps of: applying a low negative voltage to the substrate of the array; applying simultaneously an intermediate positive voltage to drain regions of selected memory cells in the array that are to be erased; and applying simultaneously a reference voltage of zero volts to control gates of the selected memory cells, said source regions being allowed to float.