Single transistor electrically programmable memory device and method

Claim 2

An electrically erasable memory device having a plurality of storage sites, a plurality of row address lines, a plurality of column address lines, and a plurality of erase lines, wherein each combination of one of the plurality of row address lines and one of the plurality of column address lines define a different one of the plurality of storage sites, and further wherein each of the plurality of storage sites comprises a single transistor including a source coupled to an associated one of the plurality of erase lines; a drain coupled to an associated one of the plurality of column address lines; a control gate coupled to an associated one of the plurality of row address lines; and a floating gate positioned between the gate and the source and drain; and further including means for injecting hot electrons onto the floating gate when the associated ones of the column address and row address lines are raised to a first predetermined potential above that of the associated one of the erase line; and means for inducing Fowler-Nordheim tunneling of electrons from the floating gate to the source when the associated erase line is raised to a second predetermined potential above the associated row address line.

Claim 3

The device of claim 1 wherein the injecting means comprise a first layer of insulating material positioned between the gate and the floating gate, said insulating material having a predetermined thickness and having a high dielectric constant to provide a high capacitance between the gate and floating gate; and a secod layer of insulating material positioned between the floating gate and the source and drain, said second layer having a thickness less than the thickness of the first layer of insulating material and which is selected so as to permit Fowler-Nordheim tunneling while optimizing the capacitive coupling between the floating gate and the source.

Claim 4

The device of claim 2 wherein the dielectric constant of the first layer is greater than 5.

Claim 5

The device of claim 3 wherein the thickness of the second layer is less than 200 angstroms.

Claim 6

The device of claim 4 wherein the second layer comprises oxynitride.

Claim 7

The device of claim 3 wherein the first layer includes tantalum pentoxide.

Claim 8

The device of claim 3 wherein the first layer includes oxide rich tantalum pentoxide.

Claim 9

The device of claim 3 wherein the first layer comprises a sandwich including a layer of tantalum pentoxide and a layer of thermal oxide.

Claim 10

The device of claim 8 wherein the tantalum pentoxide layer is approximately 500 angstroms thick.

Claim 11

The device of claim 8 wherein the thermal oxide layer is approximately 150 angstroms thick.

Claim 12

The device of claim 2 wherein the tunneling means include a source diffusion having a portion which underlies the floating gate so as to accept electrons which have tunneled through the second layer from the floating gate, said source diffusion having a smooth curvature so that gate-aided junction breakdown voltages are increased.

Claim 13

The device of claim 11 wherein the source diffusion comprises a diffusion of arsenic having a predetermined depth; and a diffusion of phosphorus having a depth which is greater than the depth of the diffusion or arsenic.

Claim 14

The device of claim 2 wherein the first layer of insulating material comprises a sandwich of tantalum pentoxide and thermal oxide, the second layer of material comprises oxynitride, and the control gate and floating gate each comprise polysilicon.

Claim 15

The device of claim 1 wherein the plurality of storage sites are arranged in an array to form rows and columns of storage sites, and further wherein the erase line associated with each of the plurality of storage sites are connected in common; the column address line for each of the storage sites in a column are connected in common; and the row address line for each of the storage sites in a row are connected in common.

Claim 16

The device of claim 14 wherein the transistors in the storage sites in each of the columns are positioned so that the source of any one transistor in a column is coupled to the source of an adjacent transistor in the same column and the drain of the one transistor is coupled to the drain of a different adjacent transistor in the same column.

Claim 17

The device of claim 1 wherein the plurality of storage sites are arranged in an array to form rows and columns of sites, in which the column address lines for each of the storage sites in a column of sites are connected in common, and the row address line for each of the storage sites in a row are connected in common, and the storge sies of each row are arranged in bytes; and further wherein the bytes of storage sites are arranged in columns of bytes; and the erase lines associated with each of the storage sites in a particular column of bytes are connected in common; so that a column of bytes can be erased at one time.

Claim 18

The device of claim 1 wherein the plurality of storage sites are arranged in an array to form rows and columns of sites, in which the storage sites of each row are arranged in bytes, the row address lines for each of the storage sites in a row are connected in common, and the column address lines for each of the storage sites in a column of sites are connected in common; and further wherein the bytes of storage sites are arranged in columns of bytes and a different one of a plurality of column select lines is associated with each column of bytes; further including a plurality of means, each associated with a particular byte and coupled to the row address line that is associated with the particular byte, for selecting the particular byte; wherein each selecting means is responsive to the column select line associated with the column in which the particular byte resides, and further wherein each selecting means is coupled to the erase lines for the storage sites in the byte with which said selecting means is associated and also coupled to the erase lines of the storage sites in an adjacent byte within the same column; so that a single byte can be erased at one time by raising the column select line for the column in which the byte to be erased resides to a first potential, floating all column address lines associated with said column, and raising the row address line for the associated adjacent byte within said column to a second potential less than said first potential.