US4376947A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrically programmable floating gate semiconductor memory device
Assignee: Texas Instruments Inc
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Filing: 1979-09-04
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Granted: 1983-03-15
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Expires: 1999-09-04
Abstract
Abstract An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the floating gate is charged through an insulator between the floating gate and the channel. A simplified process for fabrication of the devices eliminates photoresist and implant steps yet produces improved characteristics in the form of higher gain and lower body effect.
Inventors
- 👤 Te-Long Chiu
- 👤 Jih-Chang Lien
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 01:17
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
130 words
An electrically programmable, nonvolatile, floating gate semiconductor memory cell comprising: an MOS transistor device formed in a face of a semiconductor body of one type and having a deep source and a deep drain of the opposite type as well as a shallow source and shallow drain of said opposite type, a channel area between said shallow source and drain, a floating gate and a control gate overlying the channel area, the control gate larger than the floating gate and the deep source and deep drain being self-aligned with the control gate, and a region of said one type doped more heavily than said body adjacent said shallow drain occupying part of the channel area but not all of the channel area, said region being self-aligned with said floating gate.
Claim 2
Dependent Claim
130 words
An electrically programmable, nonvolatile, floating gate semiconductor memory cell comprising: an MOS transistor device formed in a face of a semiconductor body of one type and having a deep source and a deep drain of the opposite type as well as a shallow source and shallow drain of said opposite type, a channel area between said shallow source and drain, a floating gate and a control gate overlying the channel area, the control gate larger than the floating gate and the deep source and deep drain being self-aligned with the control gate, and a region of said one type doped more heavily than said body adjacent said shallow drain occupying part of the channel area but not all of the channel area, said region being self-aligned with said floating gate.
Claim 3
Dependent Claim
16 words
A cell according to claim 1 wherein the control gate and floating gate are polycrystalline silicon.
Claim 4
Dependent Claim
44 words
A cell according to claim 1 wherein a second region of said one type doped more heavily than said body is included in said channel area adjacent said shallow source occupying a part of the channel area but not all of the channel area.
References Cited (Backward Citations)
US3868187A
Cited
US4161039A
Cited
US4199996A
Cited
US4122544A
Cited
US4151021A
Cited
US4258378A
Cited
US4222063A
Cited
US4302766A
Cited
US4317273A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-03-14 | 1986-09-13 | 1987-03-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-03-14 | 1990-09-13 | 1991-03-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-03-14 | 1994-09-13 | 1995-03-15 | $7700.00 | Window Closed / Lapsed |