Patent US2572605A successfully refreshed from Google Patents.
US3744036A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrically programmable read only memory array
Assignee: Intel Corp
•
Filing: 1971-05-24
•
Granted: 1973-07-03
•
Expires: 1991-05-24
Abstract
Abstract An electrically programmable semiconductor read only memory array which utilizes a floating gate metal-oxide-semiconductor (MOS) device as a storage element is described. The floating gate of the device (storage element) may be negatively charged by avalanche injection. A field effect transistor is coupled in series with the storage element to form a single memory cell. A plurality of cells comprise an array. The gate of the field effect transistor is coupled to an X-line of the memory array and one of the other terminals of this transistor, in one embodiment, is coupled to a Y-line of the array. The array is electrically programmed by application of information to the X and Y lines of the array.
Inventors
- 👤 Bentchkowsky D Frohman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 19:40
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0433
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
167 words
A memory array comprising: a plurality of X lines; a plurality of Y lines; at least one common line; a plurality of memory cells, each comprising a storage device having a pair of spaced-apart P-type regions disposed in an Ntype substrate and a floating gate for receiving an electrical charge from said substrate, one of said regions being coupled to one of said Y lines; and a field effect transistor having a gate, a source and a drain, said gate being coupled to one of said X lines, said source being coupled to said other region of said storage device and said drain being coupled to said common line; and voltage means for applying a negative voltage to at least one of said Y lines of sufficient magnitude to cause an avalanche condition in said storage device, thereby causing an electrical charge to be injected onto said floating gate, whereby the memory array may be selectively programmed and once programmed information may be read from the array.
Claim 2
Dependent Claim
167 words
A memory array comprising: a plurality of X lines; a plurality of Y lines; at least one common line; a plurality of memory cells, each comprising a storage device having a pair of spaced-apart P-type regions disposed in an Ntype substrate and a floating gate for receiving an electrical charge from said substrate, one of said regions being coupled to one of said Y lines; and a field effect transistor having a gate, a source and a drain, said gate being coupled to one of said X lines, said source being coupled to said other region of said storage device and said drain being coupled to said common line; and voltage means for applying a negative voltage to at least one of said Y lines of sufficient magnitude to cause an avalanche condition in said storage device, thereby causing an electrical charge to be injected onto said floating gate, whereby the memory array may be selectively programmed and once programmed information may be read from the array.
Claim 3
Dependent Claim
27 words
The device defined in claim 1 wherein said floating gate of said storage device and said gate of said field effect transistor comprise a P-type polycrystalline silicon.
Claim 4
Dependent Claim
124 words
A memory array comprising: a plurality of X lines; a plurality of Y lines; a plurality of memory cells each coupled between one of said X lines and one of said Y lines and each including a storage device having a pair of spaced-apart regions of a first conductivity type disposed in a substrate of a second conductivity type and a floating gate for receiving an electrical charge from said substrate, and a diode coupled in series with said storage device; whereby voltages of sufficient magnitude may be applied to selected X lines and Y lines of said array to cause an avalanche condition in said storage devices, thereby permitting an electrical charge to be injected onto said floating gates for programming the array.
Claim 5
Dependent Claim
124 words
A memory array comprising: a plurality of X lines; a plurality of Y lines; a plurality of memory cells each coupled between one of said X lines and one of said Y lines and each including a storage device having a pair of spaced-apart regions of a first conductivity type disposed in a substrate of a second conductivity type and a floating gate for receiving an electrical charge from said substrate, and a diode coupled in series with said storage device; whereby voltages of sufficient magnitude may be applied to selected X lines and Y lines of said array to cause an avalanche condition in said storage devices, thereby permitting an electrical charge to be injected onto said floating gates for programming the array.
Claim 6
Dependent Claim
15 words
The device defined in claim 3 wherein said floating gate comprises a P-type polycrystalline silicon.
References Cited (Backward Citations)
US3500142A
Cited
US3387286A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-02 | 1977-01-01 | 1977-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-02 | 1981-01-01 | 1981-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-02 | 1985-01-01 | 1985-07-03 | $7700.00 | Window Closed / Lapsed |