Integrated circuit memory devices having nonvolatile single transistor unit cells therein

Abstract

Abstract Integrated circuit memory devices include a gate oxide insulating layer on a surface of a semiconductor substrate containing a bulk region of first conductivity type and spaced source and drain regions of second conductivity type therein extending to the surface. First and second separate control gates are also preferably provided in each unit cell and extend opposite the surface. A ferroelectric insulating layer is provided between the first and second control gates and acts as a nonvolatile data storage medium when it is polarized in a predetermined state. A floating gate is also provided having a preferred C-shape when viewed in transverse cross-section. In particular, the floating gate is provided to have a first extension disposed between the first control gate and the first electrically insulating layer and a second extension disposed between the first control gate and the ferroelectric insulating layer. The first control gate is also electrically insulated from the floating gate by a second electrically insulating layer disposed between the first control gate and the first extension and a third electrically insulating layer disposed between the first control gate and the second extension. According to a preferred aspect of the present invention, the thickness of the second electrically insulating is greater than a thickness of the third electrically insulating layer, however, the dielectric constant of the third electrically insulating layer is preferably greater than the dielectric constant of the second electrically insulating layer.

Inventors

• 👤 Keun-Ho Lee
• 👤 Chang-Hoon Choi

Bibliographic Details