US6171900B1
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CVD Ta2O5/oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFET
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1999-04-15
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Granted: 2001-01-09
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Expires: 2019-04-15
Abstract
Abstract A method of fabricating a CVD Ta 2 O 5 /Oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFETs is disclosed. In a first embodiment, the surface of a silicon substrate is reacted in N 2 O or NO ambient to form an oxynitride layer. Tantalum oxide is next chemical vapor deposited, thus forming a Ta 2 O 5 /Oxynitride stacked gate insulator. The stacked gate is then completed by depositing titanium nitride as the gate electrode and then patterning and forming the gate structure. In the second embodiment, a gate oxide is first formed on the silicon substrate. Then the gate oxide layer is nitridated in N 2 O or NO ambient to form the oxynitridated layer, thus forming a two-step oxynitride layer. The tantalum oxide layer and the titanium nitride gate electrode are formed as in the first embodiment. It is disclosed in the present invention that by replacing the conventional SiO 2 layer with a composite layer of Ta 2 O 5 /oxynitride, where the oxynitride dielectric layer is grown in a nitrogen ambient, charge trapping, interface state generation, and breakdown field distribution, the time-dependent dielectric breakdown (TDDB) of gate oxides and hence the reliability of MOSFET devices are improved substantially.
Inventors
- 👤 Shi-Chung Sun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 16:48
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01342; H10D64/01344; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D64/691; H10D64/693; H10D64/667
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
82 words
A method of fabricating a CVD Ta 2 O 5 /Oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFETs comprising the steps of: providing a semiconductor substrate; oxynitridation of the surface of said substrate to form a layer of oxynitride; forming a tantalum oxide layer over said layer of oxynitride; forming a titanium nitride layer over said tantalum oxide layer; and patterning and etching said oxynitride, tantalum oxide and titanium layers to complete the forming of said stacked gate.
Claim 2
Independent Claim
82 words
A method of fabricating a CVD Ta 2 O 5 /Oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFETs comprising the steps of: providing a semiconductor substrate; oxynitridation of the surface of said substrate to form a layer of oxynitride; forming a tantalum oxide layer over said layer of oxynitride; forming a titanium nitride layer over said tantalum oxide layer; and patterning and etching said oxynitride, tantalum oxide and titanium layers to complete the forming of said stacked gate.
Claim 3
Dependent Claim
12 words
The method of claim 1 , wherein said semiconductor substrate is silicon.
Claim 4
Dependent Claim
16 words
The method of claim 1 , wherein said surface of said substrate is a silicon surface.
Claim 5
Dependent Claim
24 words
The method of claim 1 , wherein said oxynitridation of said surface is performed by reacting N 2 O or NO at silicon surface.
Claim 6
Dependent Claim
30 words
The method of claim 1 , wherein said oxynitridation is performed in a furnace at a temperature between about 850 to 1100° C. for between about 5 to 30 minutes.
Claim 7
Dependent Claim
33 words
The method of claim 1 , wherein said oxynitridation is performed in rapid thermal chamber at a temperature between about 850 to 1100° C. for a duration between about 30 to 60 seconds.
Claim 8
Dependent Claim
19 words
The method of claim 1 , wherein the thickness of said oxynitride is between about 10 to 60 Å.
Claim 9
Dependent Claim
76 words
The method of claim 1 , wherein said forming a tantalum oxide layer is accomplished by chemical vapor deposition (CVD) at a chamber pressure between about 50 to 100 Pa, temperature between about 400° C. to 475° C. with reactant gas Ta(OC 2 H 5 ) 5 at a flow rate between about 5 to 20 sccm in a N 2 carrier gas and O 2 at a flow rate between about 10 to 40 sccm.
Claim 10
Dependent Claim
20 words
The method of claim 1 , wherein the thickness of said tantalum oxide is between about 50 to 100 Å.
Claim 11
Dependent Claim
24 words
The method of claim 1 , wherein said forming a titanium nitride layer is accomplished by sputtering of Ti in an N 2 ambient.
Claim 12
Dependent Claim
20 words
The method of claim 1 , wherein the thickness of said titanium nitride is between about 100 to 500 Å.
Claim 13
Independent Claim
94 words
A method of fabricating a CVD Ta 2 O 5 /Oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFETs comprising the steps of: providing a semiconductor substrate; forming a layer of gate oxide over said semiconductor substrate; oxynitridation of said layer of gate oxide to form a layer of two-step oxynitride; forming a tantalum oxide layer over said layer of two-step oxynitride; forming a titanium nitride layer over said tantalum oxide layer; and patterning and etching said oxynitride, tantalum oxide and titanium layers to complete the forming of said stacked gate.
Claim 14
Independent Claim
94 words
A method of fabricating a CVD Ta 2 O 5 /Oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFETs comprising the steps of: providing a semiconductor substrate; forming a layer of gate oxide over said semiconductor substrate; oxynitridation of said layer of gate oxide to form a layer of two-step oxynitride; forming a tantalum oxide layer over said layer of two-step oxynitride; forming a titanium nitride layer over said tantalum oxide layer; and patterning and etching said oxynitride, tantalum oxide and titanium layers to complete the forming of said stacked gate.
Claim 15
Dependent Claim
12 words
The method of claim 12 , wherein said semiconductor substrate is silicon.
Claim 16
Dependent Claim
41 words
The method of claim 12 , wherein said forming a layer of gate oxide over said semiconductor substrate is accomplished by thermal oxidation at a temperature between about 750 to 900° C. to a thickness between about 10 to 60 Å.
Claim 17
Dependent Claim
38 words
The method of claim 12 , wherein said oxynitridation of said layer of gate oxide to form a layer of two-step oxynitride is performed by reacting N 2 O or NO at the surface of said gate oxide.
Claim 18
Dependent Claim
43 words
The method of claim 12 , wherein said oxynitridation of said layer of gate oxide to form a layer of two-step oxynitride is performed in a furnace at a temperature between about 850 to 1100° C. for between about 5 to 30 minutes.
Claim 19
Dependent Claim
45 words
The method of claim 12 , wherein said oxynitridation of said layer of gate oxide to form a layer of two-step oxynitride is performed in a rapid thermal chamber at a temperature between about 850 to 1100° C. for between about 30 to 60 seconds.
Claim 20
Dependent Claim
20 words
The method of claim 12 , wherein the thickness of said two-step oxynitride is between about 10 to 60 Å.
Claim 21
Dependent Claim
76 words
The method of claim 12 , wherein said forming a tantalum oxide layer is accomplished by chemical vapor deposition (CVD) at a chamber pressure between about 50 to 100 Pa, temperature between about 400° C. to 475° C. with reactant gas Ta(OC 2 H 5 ) 5 at a flow rate between about 5 to 20 sccm in a N 2 carrier gas and O 2 at a flow rate between about 10 to 40 sccm.
Claim 22
Dependent Claim
20 words
The method of claim 12 , wherein the thickness of said tantalum oxide is between about 50 to 100 Å.
Claim 23
Dependent Claim
24 words
The method of claim 12 , wherein said forming a titanium nitride layer is accomplished by sputtering of Ti in an N 2 ambient.
Claim 24
Dependent Claim
20 words
The method of claim 12 , wherein the thickness of said titanium nitride is between about 100 to 500 Å.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-09 | 2004-07-10 | 2005-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-09 | 2008-07-10 | 2009-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-09 | 2012-07-10 | 2013-01-09 | $7700.00 | Window Closed / Lapsed |