Method of forming high density flash memories with MIM structure

Claim 1

A method for manufacturing a nonvolatile memory on a semiconductor substrate, said method comprising the steps of: forming a gate dielectric layer on said semiconductor substrate; forming a first polysilicon layer on said gate dielectric; forming a silicon nitride layer on said first polysilicon layer; patterning said silicon nitride layer, said first polysilicon layer and said gate dielectric layer to form a gate structure on said semiconductor substrate; performed a first thermal oxidation to form a first oxide layer on said semiconductor substrate exposed by said gate structure and simultaneously form a polyoxide layer on side walls of said gate structure; forming an isolating spacers on side walls of said gate structure; performing an ion implantation to form source and drain of said nonvolatile memory in said semiconductor substrate; performing a second thermal oxidation to form a second oxide layer on said semiconductor substrate exposed by said gate structure and said isolating spacers, wherein the dopants of said first ion implantation being driven into said semiconductor substrate; removing said silicon nitride layer, said isolating spacers, then removing said polyoxide layer and said gate dielectric that is uncovered by said gate structure; forming an undoped silicon layer along a surface of said gate structure and said second oxide layer; performing a third thermal oxidation to convert said undoped silicon layer into a third oxide layer having textured interface between said semiconductor substrate and said third oxide layer; forming a second polysilicon layer on said third oxide layer; performing a chemical mechanical polishing to polish a portion of said second polysilicon layer and the top of said third oxide on said gate structure thereby exposing said gate structure, wherein said second polysilicon is separated into two parts adjacent to said gate structure in a cross-sectional view; forming a metal-insulator-metal (MIM) structure on said polished second polysilicon layer and on said gate structure, wherein said metal-insulator-metal structure includes a first conductive layer on said polished second polysilicon layer and on said gate structure, an insulator layer on said first conductive layer, a second conductive layer on said insulator layer, said polished polysilicon layer and said gate structure and said first conductive layer are used as a floating gate, wherein said second conductive layer as control gate.

Claim 2

A method for manufacturing a nonvolatile memory on a semiconductor substrate, said method comprising the steps of: forming a gate dielectric layer on said semiconductor substrate; forming a first polysilicon layer on said gate dielectric; forming a silicon nitride layer on said first polysilicon layer; patterning said silicon nitride layer, said first polysilicon layer and said gate dielectric layer to form a gate structure on said semiconductor substrate; performed a first thermal oxidation to form a first oxide layer on said semiconductor substrate exposed by said gate structure and simultaneously form a polyoxide layer on side walls of said gate structure; forming an isolating spacers on side walls of said gate structure; performing an ion implantation to form source and drain of said nonvolatile memory in said semiconductor substrate; performing a second thermal oxidation to form a second oxide layer on said semiconductor substrate exposed by said gate structure and said isolating spacers, wherein the dopants of said first ion implantation being driven into said semiconductor substrate; removing said silicon nitride layer, said isolating spacers, then removing said polyoxide layer and said gate dielectric that is uncovered by said gate structure; forming an undoped silicon layer along a surface of said gate structure and said second oxide layer; performing a third thermal oxidation to convert said undoped silicon layer into a third oxide layer having textured interface between said semiconductor substrate and said third oxide layer; forming a second polysilicon layer on said third oxide layer; performing a chemical mechanical polishing to polish a portion of said second polysilicon layer and the top of said third oxide on said gate structure thereby exposing said gate structure, wherein said second polysilicon is separated into two parts adjacent to said gate structure in a cross-sectional view; forming a metal-insulator-metal (MIM) structure on said polished second polysilicon layer and on said gate structure, wherein said metal-insulator-metal structure includes a first conductive layer on said polished second polysilicon layer and on said gate structure, an insulator layer on said first conductive layer, a second conductive layer on said insulator layer, said polished polysilicon layer and said gate structure and said first conductive layer are used as a floating gate, wherein said second conductive layer as control gate.