US6049479A
Expired / Lapsed
US
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Operational approach for the suppression of bi-directional tunnel oxide stress of a flash cell
Assignee: Monterey Research LLC
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Filing: 1999-09-23
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Granted: 2000-04-11
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Expires: 2019-09-23
Abstract
Abstract A method of erasing a flash memory cell to suppress bi-directional tunnel oxide stress that includes applying a negative voltage to the control gate of the flash memory cell, applying a bias voltage to the substrate of the flash memory cell and applying a bias voltage to the drain of the flash memory cell that equals the bias voltage applied to the substrate minus a fraction of a diode voltage drop across the drain junction formed between the drain and the substrate. The bias voltage applied to the drain is selected so that the drain junction is not forward biased. The fraction is in the range of 20% to 80% of the diode voltage drop.
Inventors
- 👤 Timothy Thurgate
- 👤 Daniel Sobek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:19
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
137 words
A method of erasing a flash memory cell to suppress bi-directional tunnel oxide stress in the flash memory cell that includes a substrate, a source formed in the substrate and a drain formed in the substrate thereby forming a drain junction, a layer of tunnel oxide formed on a surface of the substrate, a floating gate formed on the layer of tunnel oxide, a layer of dielectric formed on the floating gate and a control gate formed on the layer of dielectric, the method comprising: applying a negative voltage to the control gate; applying a bias voltage V B to the substrate; and applying a bias voltage V D to the drain that equals the bias voltage V B applied to the substrate minus a fraction of a diode voltage drop V Diode across the drain junction.
Claim 2
Independent Claim
137 words
A method of erasing a flash memory cell to suppress bi-directional tunnel oxide stress in the flash memory cell that includes a substrate, a source formed in the substrate and a drain formed in the substrate thereby forming a drain junction, a layer of tunnel oxide formed on a surface of the substrate, a floating gate formed on the layer of tunnel oxide, a layer of dielectric formed on the floating gate and a control gate formed on the layer of dielectric, the method comprising: applying a negative voltage to the control gate; applying a bias voltage V B to the substrate; and applying a bias voltage V D to the drain that equals the bias voltage V B applied to the substrate minus a fraction of a diode voltage drop V Diode across the drain junction.
Claim 3
Dependent Claim
22 words
The method of claim 1 wherein the bias voltage V D is selected so that the drain junction is not forward biased.
Claim 4
Dependent Claim
16 words
The method of claim 2 wherein the fraction is in the range of 20% to 80%.
References Cited (Backward Citations)
US5959891A
Cited
US5828605A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-04-11 | 2003-10-11 | 2004-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-04-11 | 2007-10-11 | 2008-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-04-11 | 2011-10-11 | 2012-04-11 | $7700.00 | Window Closed / Lapsed |