Multi-state flash memory cell and method for programming single electron differences

Claim 2

A flash memory cell, comprising: a transistor with a control gate coupled to a word line, a drain region coupled to a data line, and a floating gate that stores a value that represents a number of bits of data; and wherein the floating gate comprises a number of nano-crystals of silicon implanted at a position in a gate oxide of the transistor electron injection.

Claim 3

The flash memory cell of claim 1, wherein the floating gate is disposed at a distance of approximately 60 to 100 angstroms from a surface of a semiconductor layer of the transistor.

Claim 4

The flash memory cell of claim 1, wherein the size of the conductive elements is selected so that the conductive element can trap a single electron.

Claim 5

A transistor, comprising: a layer of semiconductor material; first and second source/drain regions implanted in the semiconductor material; a gate oxide disposed outwardly from the layer of semiconductor material; a control gate disposed outwardly from the gate oxide; and a number of crystals of conductive material that are electrically isolated from each other and disposed in the oxide layer for storing data by trapping electrons when a voltage is applied to the control gate, the crystals implanted at a distance from a surface of the semiconductor material such that each crystal is capable of trapping a single electron by hot electron injection.

Claim 6

A transistor, comprising: a layer of semiconductor material; first and second source/drain regions implanted in the semiconductor material; a gate oxide disposed outwardly from the layer of semiconductor material; a control gate disposed outwardly from the gate oxide; and a number of crystals of conductive material that are electrically isolated from each other and disposed in the oxide layer for storing data by trapping electrons when a voltage is applied to the control gate, the crystals implanted at a distance from a surface of the semiconductor material such that each crystal is capable of trapping a single electron by hot electron injection.

Claim 7

The transistor of claim 4, wherein the crystals comprise crystals of semiconductor material implanted in the gate oxide.

Claim 8

The transistor of claim 4, wherein the crystals have a size such that the crystal traps at most one electron by hot electron injection.

Claim 9

The transistor of claim 4, wherein the crystals are disposed at a distance of 60 to 100 angstroms from the surface of the semiconductor layer.

Claim 10

A memory device, comprising: a first array of flash memory cells, each cell storing data on a floating gate of a transistor of the cell; a second array of flash memory cells, each cell storing the state of an associated cell of the first array for a time prior to storing data in the associated cell of the first array; the floating gates of the memory cells of the first and second arrays each comprising a number of nano-crystals disposed in a gate oxide so as to trap electrons by hot electron injection; addressing circuitry coupled to the first and second arrays for accessing associated cells of the first and second arrays; and a read circuit coupled to the first and second arrays that reads the value of associated cells of the first and second arrays and that compares the values from the cells of the first and second arrays to produce an output signal with a value that represents a number of bits of data.

Claim 11

A memory device, comprising: a first array of flash memory cells, each cell storing data on a floating gate of a transistor of the cell; a second array of flash memory cells, each cell storing the state of an associated cell of the first array for a time prior to storing data in the associated cell of the first array; the floating gates of the memory cells of the first and second arrays each comprising a number of nano-crystals disposed in a gate oxide so as to trap electrons by hot electron injection; addressing circuitry coupled to the first and second arrays for accessing associated cells of the first and second arrays; and a read circuit coupled to the first and second arrays that reads the value of associated cells of the first and second arrays and that compares the values from the cells of the first and second arrays to produce an output signal with a value that represents a number of bits of data.

Claim 12

The memory device of claim 8, wherein each memory cell includes a field-effect transistor formed on a semiconductor layer, and the nano-crystals of each floating gate are disposed at a distance of 60 to 100 angstroms from the semiconductor layer.

Claim 13

The memory device of claim 8, wherein the size of the nano-crystals is chosen such that a single electron trapped by the nano-crystal changes the voltage of the nano-crystal sufficiently so that the nano-crystal repels other electrons that approach the nano-crystal during a write operation.

Claim 14

The memory device of claim 8, wherein the nano-crystals comprise a semiconductor material.

Claim 17

The method of claim 12, wherein the step of trapping electrons comprises the step of trapping electrons with nano-crystals formed by implanting a semiconductor material in a gate oxide of the memory cell.