Patent US6664129B2 successfully refreshed from Google Patents.
US6664129B2
Expired / Lapsed
US
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Integrated circuits and methods for their fabrication
Assignee: Adeia Semiconductor Technologies LLC
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Filing: 2002-12-12
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Granted: 2003-12-16
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Expires: 2022-12-12
Abstract
Abstract To fabricate contacts on a wafer backside, openings ( 124 ) are formed in the face side of the wafer ( 104 ). A dielectric layer ( 140 ) and some contact material ( 150 ), e.g. metal, are deposited into the openings. Then the backside is etched until the contacts ( 150 C) are exposed and protrude out. The protruding portion of each contact has an outer sidewall ( 150 V). At least a portion of the sidewall is vertical or sloped outwards with respect to the opening when the contact is traced down. The contact is soldered to an another structure ( 410 ), e.g. a die or a PCB. The solder ( 420 ) reaches and at least partially covers the sidewall portion which is vertical or sloped outwards. The strength of the solder bond is improved as a result. The dielectric layer protrudes around each contact. The protruding portion ( 140 P) of the dielectric becomes gradually thinner around each contact in the downward direction. The thinned dielectric is more flexible, and is less likely detach from the contact when the contact is pulled sideways. Other embodiments are also described.
Inventors
- 👤 Oleg Siniaguine
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:23
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; H10D62/00; H10D62/10; H10D62/117; H10W; H10W20/00; H10W20/01; H10W20/021; H10W20/023; H10W20/0245; H10W20/0249; H10W20/20; H10W20/211; H10W20/212; H10W20/2125; H10W20/40; H10W90/00; H10P; H10P50/00; H10P50/20; H10P50/24; H10P50/242; H10P52/00; H10W46/00; H10W72/00; H10W72/071; H10W72/072; H10W72/20; H10W72/221; H10W72/241; H10W72/90; H10W72/921; H10W72/923; H10W90/20; H10W90/297; H10W90/701; H10W90/721; H10W90/722; H10W90/724
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
185 words
An integrated circuit fabrication method comprising: (a) forming one or more openings in a first generally horizontal surface of a semiconductor substrate; (b) forming a first dielectric and a conductor in each of the one or more openings with the conductor in each of the openings being separated from the substrate by the first dielectric; (c) removing material from a second generally horizontal surface of the substrate to expose the first dielectric and turn the one or more openings into through holes, and removing the exposed first dielectric to expose the conductor at the second surface of the substrate, such that the first dielectric forms a protrusion at each opening at the second surface, and the conductor protrudes from the first dielectric at each protrusion of the first dielectric; wherein the protruding portion of each conductor has an outer surface not covered by the dielectric, and at least a portion of the outer surface is either vertical or is sloped outwards, laterally away from the through hole in which the conductor is formed, when the surface is traced in a direction away from the substrate.
Claim 2
Dependent Claim
185 words
An integrated circuit fabrication method comprising: (a) forming one or more openings in a first generally horizontal surface of a semiconductor substrate; (b) forming a first dielectric and a conductor in each of the one or more openings with the conductor in each of the openings being separated from the substrate by the first dielectric; (c) removing material from a second generally horizontal surface of the substrate to expose the first dielectric and turn the one or more openings into through holes, and removing the exposed first dielectric to expose the conductor at the second surface of the substrate, such that the first dielectric forms a protrusion at each opening at the second surface, and the conductor protrudes from the first dielectric at each protrusion of the first dielectric; wherein the protruding portion of each conductor has an outer surface not covered by the dielectric, and at least a portion of the outer surface is either vertical or is sloped outwards, laterally away from the through hole in which the conductor is formed, when the surface is traced in a direction away from the substrate.
Claim 3
Dependent Claim
32 words
The method of claim 1 wherein the removing operation (c) comprises a simultaneous etch of the substrate and the first dielectric, such that the first dielectric is etched both vertically and horizontally.
Claim 4
Dependent Claim
55 words
The method of claim 1 further comprising attaching the protruding portion of each conductor to a first substrate with a bonding material to form a conductive bond between the conductor and the first substrate, wherein the bonding material reaches and at least partially covers said outer surface portion which is either vertical or sloped outwards.
Claim 5
Dependent Claim
39 words
The method of claim 3 wherein the bonding material comprises solder which bonds the conductor to the first substrate, wherein the solder reaches and at least partially covers said outer surface portion which is either vertical or sloped outwards.
Claim 6
Dependent Claim
19 words
The method of claim 3 wherein said portion of the protruding outer surface of the conductor is sloped outwards.
Claim 7
Dependent Claim
56 words
The method of claim 1 wherein: forming the conductor comprises forming a first conductive layer and a second conductive layer separating the first conductive layer from the dielectric; wherein the method further comprises removing the second conductive layer during and/or after the operation (c) to expose the first conductive layer at the bottom of the substrate.
Claim 8
Dependent Claim
22 words
The method of claim 6 wherein the first conductive layer is solder wettable, and the second conductive layer is not solder wettable.
Claim 9
Dependent Claim
191 words
An integrated circuit fabrication method comprising: forming one or more openings in a top surface of a semiconductor substrate, wherein each opening has a sidewall, and at least a first portion of the sidewall is either vertical or sloped outwards relative to the opening when the sidewall is traced down; forming a first dielectric and a conductor in each opening with the conductor in each opening being separated from the substrate by the first dielectric; removing material from a bottom surface of the substrate to expose the first dielectric and turn the one or more openings into through holes, and removing the exposed first dielectric to expose the conductor at the bottom surface of the substrate, such that the first dielectric forms a protrusion at each opening at the bottom surface, and the conductor protrudes from the first dielectric at each protrusion of the first dielectric; wherein the removing operation (c) removes the semiconductor material from said first portion of the sidewall of each opening, and removes the dielectric adjacent to the first sidewall portion of the opening, to expose the conductor adjacent to the first sidewall portion of the opening.
Claim 10
Dependent Claim
191 words
An integrated circuit fabrication method comprising: forming one or more openings in a top surface of a semiconductor substrate, wherein each opening has a sidewall, and at least a first portion of the sidewall is either vertical or sloped outwards relative to the opening when the sidewall is traced down; forming a first dielectric and a conductor in each opening with the conductor in each opening being separated from the substrate by the first dielectric; removing material from a bottom surface of the substrate to expose the first dielectric and turn the one or more openings into through holes, and removing the exposed first dielectric to expose the conductor at the bottom surface of the substrate, such that the first dielectric forms a protrusion at each opening at the bottom surface, and the conductor protrudes from the first dielectric at each protrusion of the first dielectric; wherein the removing operation (c) removes the semiconductor material from said first portion of the sidewall of each opening, and removes the dielectric adjacent to the first sidewall portion of the opening, to expose the conductor adjacent to the first sidewall portion of the opening.
Claim 11
Dependent Claim
32 words
The method of claim 8 wherein the removing operation (c) comprises a simultaneous etch of the substrate and the first dielectric, such that the first dielectric is etched both vertically and horizontally.
Claim 12
Dependent Claim
43 words
The method of claim 8 further comprising attaching the protruding portion of each contact to a first substrate with a bonding material which reaches and at least partially covers said exposed conductor which was adjacent to the first sidewall portion of each opening.
Claim 13
Dependent Claim
39 words
The method of claim 10 wherein the bonding material comprises solder which bonds the conductor to the first substrate, wherein the solder reaches and at least partially covers said outer surface portion which is either vertical or sloped outwards.
Claim 14
Dependent Claim
26 words
The method of claim 10 wherein said portion of the protruding outer surface of the conductor is sloped outwards; and the bonding material is anisotropic adhesive.
Claim 15
Dependent Claim
56 words
The method of claim 8 wherein: forming the conductor comprises forming a first conductive layer and a barrier layer preventing intermixing between the first conductive layer and the dielectric; wherein the method further comprises removing the barrier layer during and/or after the operation (c) to expose the first conductive layer at the bottom of the substrate.
Claim 16
Dependent Claim
22 words
The method of claim 13 wherein the first conductive layer is solder wettable, and the second conductive layer is not solder wettable.
Claim 17
Dependent Claim
132 words
An integrated circuit fabrication method comprising: forming one or more openings in a first surface of a semiconductor substrate; forming a dielectric and a conductor in each of the one or more openings with the conductor in each of the openings being separated from the substrate by the dielectric; removing material from a second surface of the substrate to expose the dielectric and turn the one or more openings into through holes, and removing the exposed dielectric to expose the conductor at the second surface of the substrate, such that at each through hole the dielectric forms a protrusion around the conductor at the second surface; wherein the removing operation comprises a simultaneous etch of the substrate and the first dielectric, such that the first dielectric is etched both vertically and horizontally.
Claim 18
Dependent Claim
132 words
An integrated circuit fabrication method comprising: forming one or more openings in a first surface of a semiconductor substrate; forming a dielectric and a conductor in each of the one or more openings with the conductor in each of the openings being separated from the substrate by the dielectric; removing material from a second surface of the substrate to expose the dielectric and turn the one or more openings into through holes, and removing the exposed dielectric to expose the conductor at the second surface of the substrate, such that at each through hole the dielectric forms a protrusion around the conductor at the second surface; wherein the removing operation comprises a simultaneous etch of the substrate and the first dielectric, such that the first dielectric is etched both vertically and horizontally.
Claim 19
Dependent Claim
18 words
The method of claim 15 wherein the conductor protrudes from the dielectric at each protrusion of the dielectric.
Claim 20
Dependent Claim
18 words
The method of claim 16 further comprising soldering the protruding portion of each conductor to a first substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-12-15 | 2007-06-16 | 2007-12-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-12-15 | 2011-06-16 | 2011-12-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-12-15 | 2015-06-16 | 2015-12-16 | $7700.00 | Window Closed / Lapsed |