US4978639A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1989-01-10
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Granted: 1990-12-18
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Expires: 2009-01-10
Abstract
Abstract Metallized via-holes and a wraparound metal plating are simultaneously formed on semiconductor chips by patterning a photoresist mask on the front surface of the wafer to open windows over metal pads as well as the grid areas where wraparound plating is desired; etching off the exposed metal if necessary and forming via-holes and grooves in the wafer by reactive ion etching to a depth which is less than the total thickness of the wafer; depositing a thin conductive film along the walls of the grooves and via-holes by electroless methods; plating the walls of the grooves and the via-holes with conductive metal by electrolytic methods; removing the back surface of the wafer ("backlapping") along with the floors of both the grooves and the via-holes, to expose the metal on the wall of the via-holes and separate the individual chips; and, depositing conductive metal on the back surface of the individual chips to complete the grounding path.
Inventors
- 👤 Chang-Hwang Hua
- 👤 Simon S. Chan
- 👤 Ding-Yuan S. Day
- 👤 Adrian C. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:14
CPC Classifications
H; H10; H10P; H10P54/00; H10P14/00; H10P14/40; H10P14/46; H10W; H10W20/00; H10W20/01; H10W20/021; H10W20/023; H10W20/0238; H10W20/0245; Y; Y10; Y10S; Y10S148/00; Y10S148/028; Y10S148/135; Y10S438/00; Y10S438/977
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
194 words
A method for simultaneously producing plated via-holes and wraparound plating in semiconductor chips formed from a semiconductor wafer having a front surface including a plurality of metal pads, a back surface, and a thickness measured from the front surface to the back surface, the method comprising the steps of: (i) forming via-holes and grooves in the wafer from its front surface, the grooves defining the boundaries of individual semiconductor chips, the grooves and the via-holes extending from the front surface of the wafer to a depth within the wafer which is less than the total thickness of the wafer, the via-holes being formed through selected metal pads, the grooves and via-holes each having walls and a floor; (ii) simultaneously plating the walls and floor of the grooves and the via-holes with conductive metal; (iii) removing a portion of the back surface of the semiconductor wafer to a depth sufficient to remove the floor of both the grooves and the via-holes, thereby exposing the metal plating located on the walls of both the via-holes and the grooves, thus separating the individual chips; and (iv) plating the back surface of the individual chips with conductive metal.
Claim 2
Independent Claim
194 words
A method for simultaneously producing plated via-holes and wraparound plating in semiconductor chips formed from a semiconductor wafer having a front surface including a plurality of metal pads, a back surface, and a thickness measured from the front surface to the back surface, the method comprising the steps of: (i) forming via-holes and grooves in the wafer from its front surface, the grooves defining the boundaries of individual semiconductor chips, the grooves and the via-holes extending from the front surface of the wafer to a depth within the wafer which is less than the total thickness of the wafer, the via-holes being formed through selected metal pads, the grooves and via-holes each having walls and a floor; (ii) simultaneously plating the walls and floor of the grooves and the via-holes with conductive metal; (iii) removing a portion of the back surface of the semiconductor wafer to a depth sufficient to remove the floor of both the grooves and the via-holes, thereby exposing the metal plating located on the walls of both the via-holes and the grooves, thus separating the individual chips; and (iv) plating the back surface of the individual chips with conductive metal.
Claim 3
Dependent Claim
48 words
The method as recited in claim 1 wherein the steps of forming the grooves and via-holes is by applying photoresist to the front surface of the wafer, exposing and developing the photoresist using a pattern to create a mask, and etching the grooves and via-holes using this mask.
Claim 4
Dependent Claim
19 words
The method as recited in claim 2 in which the grooves and via-holes are etched by reactive ion etching.
Claim 5
Dependent Claim
74 words
The method as recited in claim 1 wherein the steps of depositing the conductive metal plating on the walls and floors of the grooves and on the walls and floors of the via-holes includes the steps of electroless depositing a first layer of conductive metal on walls and floor of the grooves and the via-holes and then depositing on the first layer of conductive metal a second layer of conductive metal by electrolytic plating.
Claim 6
Dependent Claim
25 words
The method as recited in claim 4 wherein the step of depositing the first layer of conductive metal comprises electroless plating a layer of palladium.
Claim 7
Dependent Claim
36 words
The method as recited in claim 4 wherein the step of depositing the second layer of conductive metal comprises the step of electrolytically plating one or more metals selected from the group comprising gold and platinum.
Claim 8
Dependent Claim
20 words
The method as recited in claim 4 wherein the electrolytic step further comprises electrolytic plating while ultrasonically agitating the electrolyte.
Claim 9
Dependent Claim
35 words
The method as recited in claim 1 wherein the step of plating the conductive metal on the back surface of the chips comprises the step of electroless plating the back surface with the conductive metal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-17 | 1994-06-18 | 1994-12-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-17 | 1998-06-18 | 1998-12-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-17 | 2002-06-18 | 2002-12-18 | $7700.00 | Window Closed / Lapsed |