Process for fabrication of stacked, complementary MOS field effect transistor circuits

Claim 1

A method for fabricating a stacked complementary metal oxide silicon field effect transistor device comprising the steps of: depositing a layer of phosphosilicate glass on top of the gate electrode of an N channel field effect transistor device formed in the surface of a monocrystalline silicon substrate having source and drain diffusions in said substrate on either side of said gate; depositing a layer of P-type polycrystalline silicon over said phosphosilicate glass layer, extending over said source and drain diffusions and physically contacting the drain diffusion on the surface of said monocrystalline silicon substrate of said N channel device; heating said polycrystalline silicon layer including the portion contacting said substrate to a recrystallization temperature; cooling and recrystallizing said polycrystalline silicon layer into a monocrystalline silicon form having a lattice orientation epitaxially reoriented to the lattice orientation of said monocrystalline semiconductor substrate; and heating said phosphosilicate glass layer so as to diffuse phosphorus atoms from said phosphosilicate glass layer upwardly into said silicon layer, forming an N-type region which is juxtaposed with said gate electrode and is self-aligned to said gate electrode, forming the channel region of a P channel field effect transistor device, the source and drain regions of which being formed on either side of said channel region; whereby an upper, P channel field effect transistor device is formed in said silicon layer, which shares said gate electrode with said N channel device.

Claim 2

A method for fabricating a stacked complementary metal oxide silicon field effect transistor device comprising the steps of: depositing a layer of phosphosilicate glass on top of the gate electrode of an N channel field effect transistor device formed in the surface of a monocrystalline silicon substrate having source and drain diffusions in said substrate on either side of said gate; depositing a layer of P-type polycrystalline silicon over said phosphosilicate glass layer, extending over said source and drain diffusions and physically contacting the drain diffusion on the surface of said monocrystalline silicon substrate of said N channel device; heating said polycrystalline silicon layer including the portion contacting said substrate to a recrystallization temperature; cooling and recrystallizing said polycrystalline silicon layer into a monocrystalline silicon form having a lattice orientation epitaxially reoriented to the lattice orientation of said monocrystalline semiconductor substrate; and heating said phosphosilicate glass layer so as to diffuse phosphorus atoms from said phosphosilicate glass layer upwardly into said silicon layer, forming an N-type region which is juxtaposed with said gate electrode and is self-aligned to said gate electrode, forming the channel region of a P channel field effect transistor device, the source and drain regions of which being formed on either side of said channel region; whereby an upper, P channel field effect transistor device is formed in said silicon layer, which shares said gate electrode with said N channel device.

Claim 3

A method for fabricating a stacked complementary metal oxide silicon field effect transistor device comprising the steps of: depositing a layer of phosphosilicate glass on top of the gate electrode of an N channel field effect transistor device formed in the surface of a monocrystalline silicon substrate; depositing a layer of P-type polycrystalline silicon over said phosphosilicate glass layer and extending over and physically contacting the drain diffusion on the surface of said monocrystalline silicon substrate of said N channel device; heating said polycrystalline silicon layer including the portion contacting said drain region of said N channel device, to a recrystallization temperature; cooling and recrystallizing said polycrystalline silicon layer into a monocrystalline silicon form having a lattice orientation epitaxially reoriented to the lattice orientation of said monocrystalline semiconductor substrate; and heating said phosphosilicate glass layer so as to diffuse phosphorus atoms from said first phosphosilicate glass layer upwardly into said silicon layer, forming an N-type region which is juxtaposed with said gate electrode and is self-aligned to said gate electrode, forming the channel region of a P channel field effect transistor device, the source and drain regions of which being formed on either side of said channel regions; whereby an upper, P channel field effect transistor device is formed in said silicon layer, which shares said gate electrode with said N channel device.

Claim 4

A method for fabricating a stacked complementary metal oxide silicon field effect transistor device comprising the steps of: depositing a layer of phosphosilicate glass on top of the gate electrode of an N channel field effect transistor device formed in the surface of a monocrystalline silicon substrate; depositing a layer of P-type polycrystalline silicon over said phosphosilicate glass layer and extending over and physically contacting the drain diffusion on the surface of said monocrystalline silicon substrate of said N channel device; heating said polycrystalline silicon layer including the portion contacting said drain region of said N channel device, to a recrystallization temperature; cooling and recrystallizing said polycrystalline silicon layer into a monocrystalline silicon form having a lattice orientation epitaxially reoriented to the lattice orientation of said monocrystalline semiconductor substrate; and heating said phosphosilicate glass layer so as to diffuse phosphorus atoms from said first phosphosilicate glass layer upwardly into said silicon layer, forming an N-type region which is juxtaposed with said gate electrode and is self-aligned to said gate electrode, forming the channel region of a P channel field effect transistor device, the source and drain regions of which being formed on either side of said channel regions; whereby an upper, P channel field effect transistor device is formed in said silicon layer, which shares said gate electrode with said N channel device.

Claim 5

A method for fabricating a stacked complementary metal oxide silicon field effect transistor device comprising the steps of: depositing a layer of phosphosilicate glass on top of the gate electrode of an N channel field effect transistor device formed in the surface of a monocrystalline silicon substrate having source and drain diffusions in said substrate on either side of said gate; depositing a layer of polycrystalline silicon over said phosphosilicate glass layer, extending over said source and drain diffusions and physically contacting the drain diffusion on the surface of said monocrystalline silicon substrate of said N channel device; heating said polycrystalline silicon layer including the portion contacting said substrate to a recrystallization temperature; cooling and recrystallizing said polycrystalline silicon layer into a monocrystalline silicon form having a lattice orientation epitaxially reoriented to the lattice orientation of said monocrystalline semiconductor substrate; heating said phosphosilicate glass layer so as to diffuse phosphorus atoms from said phosphosilicate glass layer upwardly into said silicon layer, forming an N-type region which is juxtaposed with said gate electrode and is self-aligned to said gate electrode; and doping regions in said silicon layer on both sides of said gate of said N channel device as P-type, forming respective source and drain regions of an upper, P channel field effect transistor device in said silicon layer; whereby said upper P channel device shares the same gate with said lower N channel device.

Claim 6

A method for fabricating a stacked complementary metal oxide silicon field effect transistor device comprising the steps of: depositing a layer of phosphosilicate glass on top of the gate electrode of an N channel field effect transistor device formed in the surface of a monocrystalline silicon substrate having source and drain diffusions in said substrate on either side of said gate; depositing a layer of polycrystalline silicon over said phosphosilicate glass layer, extending over said source and drain diffusions and physically contacting the drain diffusion on the surface of said monocrystalline silicon substrate of said N channel device; heating said polycrystalline silicon layer including the portion contacting said substrate to a recrystallization temperature; cooling and recrystallizing said polycrystalline silicon layer into a monocrystalline silicon form having a lattice orientation epitaxially reoriented to the lattice orientation of said monocrystalline semiconductor substrate; heating said phosphosilicate glass layer so as to diffuse phosphorus atoms from said phosphosilicate glass layer upwardly into said silicon layer, forming an N-type region which is juxtaposed with said gate electrode and is self-aligned to said gate electrode; and doping regions in said silicon layer on both sides of said gate of said N channel device as P-type, forming respective source and drain regions of an upper, P channel field effect transistor device in said silicon layer; whereby said upper P channel device shares the same gate with said lower N channel device.

Claim 7

A method for fabricating a stacked complementry metal oxide silicon field effect transistor device comprising the steps of: depositing a layer of phosphosilicate glass on top of the gate electrode of an N channel field effect transistor device formed in the surface of a monocrystalline silicon substrate having source and drain diffusions in said substrate on either side of said gate; depositing a layer of P-type polycrystalline silicon over said phosphosilicate glass layer, extending over said source and drain diffusions and physically contacting the drain diffusion on the surface of said monocrystalline silicon substrate of said N channel device; heating said polycrystalline silicon layer including the portion contacting said substrate to a recrystallization temperature and heating said phosphosilicate glass layer so as to diffuse phosphorus atoms from said phosphosilicate glass layer upwardly into said silicon layer, forming an N-type region which is juxtaposed with said gate electrode and is self-aligned to said gate electrode, forming the channel region of a P channel field effect transistor device, the source and drain regions of which being formed on either side of said channel region; and cooling and recrystallizing said polycrystalline silicon layer into a monocrystalline silicon form having a lattice orientation epitaxially reoriented to the lattice orientation of said monocrystalline semiconductor substrate; whereby an upper, P channel field effect transistor device is formed in said silicon layer, which shares said gate electrode with said N channel device.

Claim 8

A method for fabricating a stacked complementry metal oxide silicon field effect transistor device comprising the steps of: depositing a layer of phosphosilicate glass on top of the gate electrode of an N channel field effect transistor device formed in the surface of a monocrystalline silicon substrate having source and drain diffusions in said substrate on either side of said gate; depositing a layer of P-type polycrystalline silicon over said phosphosilicate glass layer, extending over said source and drain diffusions and physically contacting the drain diffusion on the surface of said monocrystalline silicon substrate of said N channel device; heating said polycrystalline silicon layer including the portion contacting said substrate to a recrystallization temperature and heating said phosphosilicate glass layer so as to diffuse phosphorus atoms from said phosphosilicate glass layer upwardly into said silicon layer, forming an N-type region which is juxtaposed with said gate electrode and is self-aligned to said gate electrode, forming the channel region of a P channel field effect transistor device, the source and drain regions of which being formed on either side of said channel region; and cooling and recrystallizing said polycrystalline silicon layer into a monocrystalline silicon form having a lattice orientation epitaxially reoriented to the lattice orientation of said monocrystalline semiconductor substrate; whereby an upper, P channel field effect transistor device is formed in said silicon layer, which shares said gate electrode with said N channel device.

Claim 9

A method for fabricating a stacked complementary metal oxide silicon field effect transistor device comprising the steps of: depositing a layer of phosphosilicate glass on top of the gate electrode of an N channel field effect transistor device formed in the surface of a monocrysalline silicon substrate; deposition a layer of P-type polycrystalline silicon over said phosphosilicate glass layer and extending over and physically contacting the drain diffusion on the surface of said monocrystalline silicon substrate of said N channel device; heating said polycrystalline silicon layer including that portion contacting said drain region of said N channel device, to a recrystallization temperature and heating said phosphosilicate glass layer so as to diffuse phosphorus atoms from said first phosphosilicate glass layer upwardly into said silicon layer, forming an N-type region which is juxtaposed with said gate electrode and is self-aligned to said gate electrode; and cooling and recrystallizing said polycrystalline silicon layer into a monocrystalline silicon form having a lattice orientation epitaxially reoriented to the lattice orientation of said monocrystalline semiconductor substrate; whereby an upper, P channel field effect transistor device is formed in said silicon layer, which shares said gate electrode with said N channel device.

Claim 10

A method for fabricating a stacked complementary metal oxide silicon field effect transistor device comprising the steps of: depositing a layer of phosphosilicate glass on top of the gate electrode of an N channel field effect transistor device formed in the surface of a monocrysalline silicon substrate; deposition a layer of P-type polycrystalline silicon over said phosphosilicate glass layer and extending over and physically contacting the drain diffusion on the surface of said monocrystalline silicon substrate of said N channel device; heating said polycrystalline silicon layer including that portion contacting said drain region of said N channel device, to a recrystallization temperature and heating said phosphosilicate glass layer so as to diffuse phosphorus atoms from said first phosphosilicate glass layer upwardly into said silicon layer, forming an N-type region which is juxtaposed with said gate electrode and is self-aligned to said gate electrode; and cooling and recrystallizing said polycrystalline silicon layer into a monocrystalline silicon form having a lattice orientation epitaxially reoriented to the lattice orientation of said monocrystalline semiconductor substrate; whereby an upper, P channel field effect transistor device is formed in said silicon layer, which shares said gate electrode with said N channel device.

Claim 11

A method for fabricating a stacked complementary metal oxide silicon field effect transistor device comprising the steps of: depositing a layer of phosphosilicate glass on top of the gate electrode of an N channel field effect transistor device formed in the surface of a monocrystalline silicon substrate having source and drain diffusions in said substrate on either side of said gate; depositing a layer of polycrystalline silicon over said phosphosilicate glass layer, extending over said source and drain diffusions and physically contacting the drain diffusion on the surface of said monocrystalline silicon substrate of said N channel device; heating said polycrystalline silicon layer including the portion contacting said substrate to a recrystallization temperature and heating said phosphosilicate glass layer so as to diffuse phosphorus atoms from said phosphosilicate glass layer upwardly into said silicon layer, forming an N-type region which is juxtaposed with said gate electrode and is self-aligned to said gate electrode; cooling and recrystallizing said polycrystalline silicon layer into a monocrystalline silicon form having a lattice orientation epitaxially reoriented to the lattice orientation of said monocrystalline semiconductor substrate; and doping regions in said silicon layer on both sides of said gate of said N channel device as P-type, forming respective source and drain regions of an upper, P channel field effect transistor device in said silicon layer; whereby said upper P channel device shares the same gate with said lower N channel device.

Claim 12

A method for fabricating a stacked complementary metal oxide silicon field effect transistor device comprising the steps of: depositing a layer of phosphosilicate glass on top of the gate electrode of an N channel field effect transistor device formed in the surface of a monocrystalline silicon substrate having source and drain diffusions in said substrate on either side of said gate; depositing a layer of polycrystalline silicon over said phosphosilicate glass layer, extending over said source and drain diffusions and physically contacting the drain diffusion on the surface of said monocrystalline silicon substrate of said N channel device; heating said polycrystalline silicon layer including the portion contacting said substrate to a recrystallization temperature and heating said phosphosilicate glass layer so as to diffuse phosphorus atoms from said phosphosilicate glass layer upwardly into said silicon layer, forming an N-type region which is juxtaposed with said gate electrode and is self-aligned to said gate electrode; cooling and recrystallizing said polycrystalline silicon layer into a monocrystalline silicon form having a lattice orientation epitaxially reoriented to the lattice orientation of said monocrystalline semiconductor substrate; and doping regions in said silicon layer on both sides of said gate of said N channel device as P-type, forming respective source and drain regions of an upper, P channel field effect transistor device in said silicon layer; whereby said upper P channel device shares the same gate with said lower N channel device.

Claim 13

A method for fabricating a stacked complementary metal oxide silicon field effect transistor device comprising the steps of: depositing a layer of phosphosilicate glass on top of the gate electrode of an N channel field effect transistor device formed in the surface of a monocrystalline silicon substrate; depositing a layer of P-type polycrystalline silicon over said phosphosilicate glass layer and extending over and physically contacting the drain diffusion on the surface of said monocrystalline silicon substrate of said N channel device; heating said polycrystalline silicon layer including the portion contacting said drain region of said N channel device to a recrystallization temperature; cooling and recrystallizing said polycrystalline silicon layer into a monocrystalline silicon form having a lattice orientation epitaxially reoriented to the lattice orientation of said monocrystalline semiconductor substrate; heating said phosphosilicate glass layer so as to diffuse phosphorus atoms from said first phosphosilicate glass layer upwardly into said silicon layer, forming an N-type region which is juxtaposed with said gate electrode and is self-aligned to said gate electrode; and selectively etching the portion of said silicon layer in said drain region of said N-type device to selectively sever the electrical connection therewith; whereby an upper, P channel field effect transistor device is formed in said silicon layer, which shares said gate electrode with said N channel device and whose drain selectively makes electrical contact with said drain of said N channel device selectively forming a complementary metal oxide silicon inverter.

Claim 14

A method for fabricating a stacked complementary metal oxide silicon field effect transistor device comprising the steps of: depositing a layer of phosphosilicate glass on top of the gate electrode of an N channel field effect transistor device formed in the surface of a monocrystalline silicon substrate; depositing a layer of P-type polycrystalline silicon over said phosphosilicate glass layer and extending over and physically contacting the drain diffusion on the surface of said monocrystalline silicon substrate of said N channel device; heating said polycrystalline silicon layer including the portion contacting said drain region of said N channel device to a recrystallization temperature; cooling and recrystallizing said polycrystalline silicon layer into a monocrystalline silicon form having a lattice orientation epitaxially reoriented to the lattice orientation of said monocrystalline semiconductor substrate; heating said phosphosilicate glass layer so as to diffuse phosphorus atoms from said first phosphosilicate glass layer upwardly into said silicon layer, forming an N-type region which is juxtaposed with said gate electrode and is self-aligned to said gate electrode; and selectively etching the portion of said silicon layer in said drain region of said N-type device to selectively sever the electrical connection therewith; whereby an upper, P channel field effect transistor device is formed in said silicon layer, which shares said gate electrode with said N channel device and whose drain selectively makes electrical contact with said drain of said N channel device selectively forming a complementary metal oxide silicon inverter.

Claim 15

A method for fabricating stacked complementary metal oxide silicon field effect transistor device comprising the steps of: depositing a layer of phosphosilicate glass on top of the gate electrode fo an N channel field effect transistor device formed in the surface of a monocrystalline silicon substrate; depositing a layer of P-type polycrystalline silicon over said phosphosilicate glass layer and extending over and physically contacting the drain diffusion on the surface of said monocrystalline silicon substrate of said N channel FET device; heating said polycrystalline silicon layer including the portion contacting said drain region of said N channel device, to a recrystallization temperature and heating said phosphosilicate glass layer as to diffuse phosphorus atoms from said first phosphosilicate glass layer upwardly into said silicon layer, forming an N-type region which is juxtaposed with said gate electrode and self-aligned to said gate electrode; cooling and recrystallizing said polycrystalline silicon layer into a monocrystalline silicon form having a lattice orientation epitaxially reoriented to the lattice orientation of said monocrystalline semiconductor substrate; and selectively etching the portion of said silicon layer in said drain region of said N channel device to selectively sever the electrical connection therewith; whereby an upper, P channel field effect transistor device is formed in said silicon layer, which shares said gate electrode with said N channel device and whose drain selectively makes electrical contact with said drain of said N channel device selectively forming a complementary metal oxide silicon inverter.

Claim 16

A method for fabricating stacked complementary metal oxide silicon field effect transistor device comprising the steps of: depositing a layer of phosphosilicate glass on top of the gate electrode fo an N channel field effect transistor device formed in the surface of a monocrystalline silicon substrate; depositing a layer of P-type polycrystalline silicon over said phosphosilicate glass layer and extending over and physically contacting the drain diffusion on the surface of said monocrystalline silicon substrate of said N channel FET device; heating said polycrystalline silicon layer including the portion contacting said drain region of said N channel device, to a recrystallization temperature and heating said phosphosilicate glass layer as to diffuse phosphorus atoms from said first phosphosilicate glass layer upwardly into said silicon layer, forming an N-type region which is juxtaposed with said gate electrode and self-aligned to said gate electrode; cooling and recrystallizing said polycrystalline silicon layer into a monocrystalline silicon form having a lattice orientation epitaxially reoriented to the lattice orientation of said monocrystalline semiconductor substrate; and selectively etching the portion of said silicon layer in said drain region of said N channel device to selectively sever the electrical connection therewith; whereby an upper, P channel field effect transistor device is formed in said silicon layer, which shares said gate electrode with said N channel device and whose drain selectively makes electrical contact with said drain of said N channel device selectively forming a complementary metal oxide silicon inverter.