US4996587A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated semiconductor chip package
Assignee: International Business Machines Corp
•
Filing: 1990-03-23
•
Granted: 1991-02-26
•
Expires: 2010-03-23
Abstract
Abstract A semiconductor package utilizing a carrier with substantially parallel top and bottom surfaces having a recess in the bottom surface and a slot in the top surface communicating with the recess in the bottom surface and provided with electrical conductors on its top surface is provided with an integrated semiconductor chip having a major surface and contact pads on the major surface in the recess of the carrier, with said contact pads positioned in the region of said slot so that the contact pads can be connected by lead wires passing through said slot, to the conductors on the top side of the carrier. The active surface of the chip containing the contact pads is encapsulated but the back surface of the chip and carrier is left exposed to improve the thermal characteristics of the chip while maintaining a low package profile.
Inventors
- 👤 Kurt Hinrichsmeyer
- 👤 Werner Straehle
- 👤 Gordon A. Kelley, Jr.
- 👤 Richard W. Noth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:17
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/699; H10W90/00; H10W90/701; H10W72/00; H10W72/50; H10W72/531; H10W72/5363; H10W72/5366; H10W72/541; H10W72/5445; H10W72/851; H10W72/853; H10W72/865; H10W90/721; H10W90/722; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
111 words
A semiconductor package comprising: a chip carrier with substantially parallel top and bottom surfaces, a recess in the bottom surface, at least one slot in the top surface substantially smaller than said recess communicating with the recess in the bottom surface, electrical conductors arranged at least on the top surface of said carrier, in integrated semiconductor chip having a major surface and contact pads on said major surface arranged in the recess of said carrier with said contact pads positioned in the region of said slot, and lead wires passing through said lot in connecting the contact pads on the chip to the conductors on the top side of the carrier.
Claim 2
Dependent Claim
111 words
A semiconductor package comprising: a chip carrier with substantially parallel top and bottom surfaces, a recess in the bottom surface, at least one slot in the top surface substantially smaller than said recess communicating with the recess in the bottom surface, electrical conductors arranged at least on the top surface of said carrier, in integrated semiconductor chip having a major surface and contact pads on said major surface arranged in the recess of said carrier with said contact pads positioned in the region of said slot, and lead wires passing through said lot in connecting the contact pads on the chip to the conductors on the top side of the carrier.
Claim 3
Dependent Claim
23 words
The package of claim 1 wherein the backside of the chip and the bottom surface of the carrier lie in the same plane.
Claim 4
Dependent Claim
11 words
The package of claim 2 wherein the slot edges are beveled.
Claim 5
Dependent Claim
37 words
The package of claim 3 wherein the carrier with the embedded chip has a thickness of 0.8 to 1.2 millimeters and the thickness of the carrier in the region of the recess is 0.2 to 0.5 millimeters.
Claim 6
Dependent Claim
15 words
The package as claimed in claim 4 wherein the carrier is made of reinforced polyimide.
Claim 7
Dependent Claim
13 words
The package of claim 4 wherein the carrier is made of ceramic material.
Claim 8
Dependent Claim
17 words
The package of claim 4 wherein passive and active components are arranged on the carrier top surface.
Claim 9
Dependent Claim
115 words
A stack of packages wherein each package comprises a chip carrier with substantially parallel top and bottom surfaces, a recess in the bottom surface, at least one slot in the top surface substantially smaller than said recess communicating with the recess in the bottom surface, electrical conductors arranged at least on the top surface of said carrier, an integrated semiconductor chip having a major surface and contact pads on said major surface arranged in the recess of said carrier with said contact pads positioned in the region of said slot, and lead wires passing through said slot in connecting the contact pads on the chip to the conductors on the top side of the carrier.
Claim 10
Dependent Claim
115 words
A stack of packages wherein each package comprises a chip carrier with substantially parallel top and bottom surfaces, a recess in the bottom surface, at least one slot in the top surface substantially smaller than said recess communicating with the recess in the bottom surface, electrical conductors arranged at least on the top surface of said carrier, an integrated semiconductor chip having a major surface and contact pads on said major surface arranged in the recess of said carrier with said contact pads positioned in the region of said slot, and lead wires passing through said slot in connecting the contact pads on the chip to the conductors on the top side of the carrier.
Claim 11
Dependent Claim
123 words
A semiconductor package comprising: a chip carrier with substantially parallel top and bottom surfaces, at least two recesses in the bottom surface, at least two slots in the top surface of said carrier, each slot communicating with a respective recess in the bottom surface, electrical conductors arranged on the top surface of said carrier, an integrated semiconductor chip having a major surface and contact pads on said major surface arranged in each recess in said carrier, the contact pads of the respective chip in the recess positioned in the region of the slot communicating with the recess, lead wires passing through each said slot and connecting the contact pads on each said chip to the conductors on the top side of the carrier.
Claim 12
Dependent Claim
123 words
A semiconductor package comprising: a chip carrier with substantially parallel top and bottom surfaces, at least two recesses in the bottom surface, at least two slots in the top surface of said carrier, each slot communicating with a respective recess in the bottom surface, electrical conductors arranged on the top surface of said carrier, an integrated semiconductor chip having a major surface and contact pads on said major surface arranged in each recess in said carrier, the contact pads of the respective chip in the recess positioned in the region of the slot communicating with the recess, lead wires passing through each said slot and connecting the contact pads on each said chip to the conductors on the top side of the carrier.
References Cited (Backward Citations)
US3877064A
Cited
US4538210A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-25 | 1994-08-27 | 1995-02-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-25 | 1998-08-27 | 1999-02-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-25 | 2002-08-27 | 2003-02-26 | $7700.00 | Window Closed / Lapsed |