Three-dimensional multichip package and methods of fabricating

Claim 1

A process for fabricating a three-dimensional multichip array package having an integrated circuit (IC) master semiconductor device supporting and interconnected with a densely stacked array of subordinate integrated circuit semiconductor devices, comprising: fabricating interconnected integrated circuitry elements electrically connected to a plurality of contact terminal pads arranged in an inner peripheral row on a master semiconductor substrate to form a master device; forming a plurality of lead terminal pads on the master device arranged in an outer peripheral row and electrically connected to the inner row of contact terminal pads; forming an insulating layer of an organic material over the surface of the master device; etching openings over the contact terminal pads and the lead terminal pads; depositing a barrier metal layer and a gold layer over the contact terminal pads; fabricating interconnected integrated circuitry elements that are electrically connected to contact terminal pads arranged in a peripheral row on subordinate semiconductor substrate to form a plurality of subordinate integrated circuit semiconductor devices, the pattern of the contact pad terminals matching the pattern of the contact pad terminals on the master devices; depositing an insulating layer of an organic material over the surfaces of each subordinate integrated circuit semiconductor devices; etching control openings through each of the contact terminal pads and substrates of the plurality of subordinate semiconductor devices, the central openings of a size less than the size of the contact terminal pads; depositing a thin conformed dielectric layer over the surfaces of said subordinate semiconductor devices and on the surfaces of the central openings; anisotropically etching away the conformed dielectric layer on the surfaces of said subordinate semiconductor devices and the top edges of the dielectric layer in the central openings to a depth sufficient to expose edge surfaces of the contact terminal pads; stacking the plurality of said subordinate semiconductor devices on said master semiconductor devices with the central openings of said subordinate semiconductor devices aligned over the row of contact terminal pads on the master semiconductor device; and filling the openings with a conductive material to electrically interconnect the plurality of subordinate semiconductor devices and the master semiconductor device.