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US5155067A Expired / Lapsed US ⏱️ 0.0 years remaining

Packaging for a semiconductor die

Assignee: Micron Technology Inc
•
Filing: 1991-03-26
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Granted: 1992-10-13
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Expires: 2011-03-26
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Abstract

Abstract Disclosed is a means for packaging a plurality of semiconductor die into one component. Present designs comprise multiple singulated unpackaged die which have been probed, but not rigorously tested for complete functionality and adherence to required operating specifications. The yields of present designs of multi-chip modules (MCMs) are low and functional units are therefore costly. Unlike present designs incorporating multiple die, the inventive design comprises devices which have been singulated, packaged, and thoroughly tested for functionality and adherence to required specifications. A plurality of packaged devices are then received by a housing. The conductive leads of the packaged devices are electrically coupled with pads manufactured into the housing. These pads are enjoined with traces within the housing, which terminate externally to the housing. Input/output leads are then electrically coupled with the traces, or are coupled with the traces as the housing is manufactured. The I/O leads provide means for connection of the housing with the electronic device into which it is installed. A lid received by the housing hermetically seals the packaged die in the housing, and prevents moisture or other contaminants which may impede the proper functionality of the die from entering the housing.

Inventors

  • 👤 Alan G. Wood
  • 👤 Eugene H. Cloud
  • 👤 Larry D. Kinsman

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 16:16
CPC Classifications
H; H10; H10W; H10W90/00; H10W70/00; H10W70/40; H10W70/60

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 124 words
A method for manufacturing a semiconductor component including the steps of: a) fabricating a plurality of semiconductor die; b) enclosing each of said die in a separate package, said packages having input/output leads which allow data to be written to and read from each of said die; c) testing each of said packages for adherence to predetermined specifications, rejecting said packages which fail said tests and retaining said packages which pass said tests; d) fabricating a housing to encase said passing packages, said housing having bond pads and traces, said bond pads electrically coupled with said traces; e) coupling said input/output leads electrically with said bond pads; and f) attaching a lid to said housing thereby obstructing the passage of contaminants into said housing.
Claim 2
Independent Claim 124 words
A method for manufacturing a semiconductor component including the steps of: a) fabricating a plurality of semiconductor die; b) enclosing each of said die in a separate package, said packages having input/output leads which allow data to be written to and read from each of said die; c) testing each of said packages for adherence to predetermined specifications, rejecting said packages which fail said tests and retaining said packages which pass said tests; d) fabricating a housing to encase said passing packages, said housing having bond pads and traces, said bond pads electrically coupled with said traces; e) coupling said input/output leads electrically with said bond pads; and f) attaching a lid to said housing thereby obstructing the passage of contaminants into said housing.
Claim 3
Dependent Claim 49 words
The method of claim 1 further comprising the step of electrically coupling a second package to a second set of bond pads so that the plane of said second package is superior to the plane of a first package which is coupled with a first set of bond pads.
Claim 4
Dependent Claim 23 words
The method of claim 2 wherein said input/output leads of said second package are longer than said input/output leads of said first package.
Claim 5
Dependent Claim 47 words
The method of claim 1 further comprising the step of electrically coupling input/output leads of a second superiorly positioned package to said input/output leads of a first inferiorly positioned package, wherein said input/output leads of said first package are coupled with said bond pads of said housing.
Claim 6
Dependent Claim 36 words
The method of claim 4 wherein each of said packages have at least two input/output leads which allow, through coding, the selection of a single package thereby allowing data transfer to each of said packages individually.
Claim 7
Dependent Claim 13 words
The method of claim 5 wherein said die include static random access memory.
Claim 8
Dependent Claim 13 words
The method of claim 5 wherein said die include dynamic random access memory.
Claim 9
Dependent Claim 10 words
The method of claim 1 wherein said housing comprises plastic.
Claim 10
Dependent Claim 10 words
The method of claim 1 wherein said housing comprises ceramic.

References Cited (Backward Citations)

US4709122A Cited
US4663833A Cited
US4640436A Cited
US4943844A Cited
US4992850A Cited
US4996587A Cited
US5008734A Cited
US5036381A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-10-13 1996-04-13 1996-10-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-10-13 2000-04-13 2000-10-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-10-13 2004-04-13 2004-10-13 $7700.00 Window Closed / Lapsed

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