US5399898A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-chip semiconductor arrangements using flip chip dies
Assignee: LSI Corp
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Filing: 1992-11-12
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Granted: 1995-03-21
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Expires: 2012-11-12
Abstract
Abstract Multi-chip, multi-tier semiconductor arrangements based upon single and double-sided flip-chips are described. The double-sided flip chips provide raised bump contact means on both major surfaces of a die and provided connections to internal signals within the die, feed through connections between contacts on opposite sides of the die, and jumpered connections between contacts on the same side of the die. Various multi-chip configurations are described. Certain of these flip-chip configuration dramatically increase the ratio of I/O area (periphery) to footprint area, permitting larger numbers of I/O points within a given assembly footprint than would otherwise be possible in a single die configuration.
Inventors
- 👤 Michael D. Rostoker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:46
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/70; G03F7/70425; G03F7/70433; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/392; H; H10; H10D; H10D62/00; H10D62/10; H10D62/117; H10D89/00; H10D89/10; H10W; H10W70/00; H10W70/40; H10W70/411; H10W70/421; H10W70/435; H10W72/00; H10W72/90; H10W74/00; H10W74/10; H10W74/111; H10W74/124; H10W72/071; H10W72/075; H10W72/07551; H10W72/07554; H10W72/20; H10W72/29; H10W72/50; H10W72/531; H10W72/5363; H10W72/541; H10W72/5449; H10W72/551; H10W72/552; H10W72/5522; H10W72/59; H10W72/851; H10W72/853; H10W72/859; H10W72/874; H10W72/884; H10W72/931; H10W72/932; H10W90/00; H10W90/701; H10W90/721; H10W90/722; H10W90/724
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
140 words
A double-sided semiconductor die, comprising: a single-layer semiconductor die having a first surface and a second surface opposite the first surface; circuit elements formed within the first surface; a first plurality of raised bump contacts disposed on the first surface, and connected to the circuit elements; a second plurality of raised bump contacts disposed on the a second surface, at least a one portion of the second plurality of raised bump contacts connected through the die to the circuit elements on the first surface of the die; and conductive vias connecting at least one of the first plurality of raised bump contacts to at least one of the second plurality of raised bump contacts, said conductive vias consisting of conductive cores surrounded by insulation and disposed through holes formed in the die from the first surface to the second surface.
Claim 2
Dependent Claim
140 words
A double-sided semiconductor die, comprising: a single-layer semiconductor die having a first surface and a second surface opposite the first surface; circuit elements formed within the first surface; a first plurality of raised bump contacts disposed on the first surface, and connected to the circuit elements; a second plurality of raised bump contacts disposed on the a second surface, at least a one portion of the second plurality of raised bump contacts connected through the die to the circuit elements on the first surface of the die; and conductive vias connecting at least one of the first plurality of raised bump contacts to at least one of the second plurality of raised bump contacts, said conductive vias consisting of conductive cores surrounded by insulation and disposed through holes formed in the die from the first surface to the second surface.
Claim 3
Dependent Claim
24 words
A double-sided semiconductor die according to claim 1, further comprising: conductive jumpers forming electrical connections between some of the first or second bump contacts.
Claim 4
Dependent Claim
27 words
A double-sided semiconductor die according to claim 2, wherein: at least one conductive jumper is disposed on an insulating layer disposed on a surface of the die.
Claim 5
Dependent Claim
152 words
A flip-chip die assembly with increased bond pad density within a given footprint area, comprising: a first semiconductor die having a first surface, a peripheral area of the first surface, and a second surface opposite the first surface; first bond pads disposed in the peripheral area of the first surface; at least one second semiconductor die having a top surface, a bottom surface, and a peripheral area of the top surface, said at least one second semiconductor die being smaller than said first semiconductor die and mounted by its bottom surface to the first surface of the first semiconductor die, whereby the first bond pads remain exposed; and second bond pads disposed on the top surface of the at least one second semiconductor die along the peripheral area thereof, wherein the first and second bond pads provide for making external connections to the first and at least one second semiconductor dies, respectively.
Claim 6
Dependent Claim
152 words
A flip-chip die assembly with increased bond pad density within a given footprint area, comprising: a first semiconductor die having a first surface, a peripheral area of the first surface, and a second surface opposite the first surface; first bond pads disposed in the peripheral area of the first surface; at least one second semiconductor die having a top surface, a bottom surface, and a peripheral area of the top surface, said at least one second semiconductor die being smaller than said first semiconductor die and mounted by its bottom surface to the first surface of the first semiconductor die, whereby the first bond pads remain exposed; and second bond pads disposed on the top surface of the at least one second semiconductor die along the peripheral area thereof, wherein the first and second bond pads provide for making external connections to the first and at least one second semiconductor dies, respectively.
Claim 7
Dependent Claim
36 words
A flip-chip die assembly with increased bond pad density within a given footprint area according to claim 4, further comprising: a substrate; wherein: the second surface of the first semiconductor die is mounted to the substrate.
Claim 8
Dependent Claim
53 words
A flip-chip die assembly with increased bond pad density within a given footprint area according to claim 5, wherein: the first semiconductor die is a double-sided flip-chip die; the substrate has conductive pads disposed on a mounting surface thereof; and the first semiconductor die is mounted to the conductive pads on the substrate.
Claim 9
Dependent Claim
28 words
A flip-chip die assembly with increased bond pad density within a given footprint area according to claim 4, wherein: the second semiconductor die is a double-sided flip-chip die.
Claim 10
Dependent Claim
36 words
A flip-chip die assembly with increased bond pad density within a given footprint area according to claim 4, wherein: a ratio of aggregate peripheral area to footprint area is achieved which is in excess of 5:1.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-20 | 1998-09-19 | 1999-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-20 | 2002-09-19 | 2003-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-20 | 2006-09-19 | 2007-03-21 | $7700.00 | Window Closed / Lapsed |