US4982265A
Expired / Lapsed
US
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Semiconductor integrated circuit device and method of manufacturing the same
Assignee: Hitachi Ltd
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Filing: 1988-06-22
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Granted: 1991-01-01
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Expires: 2008-06-22
Abstract
Abstract In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
Inventors
- 👤 Masayuki Watanabe
- 👤 Toshio Sugano
- 👤 Seiichiro Tsukui
- 👤 Takashi Ono
- 👤 Yoshiaki Wakashima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:11
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/02; H05K1/14; H05K1/141; G; G11; G11C; G11C5/00; G11C5/06; G11C8/00; G11C8/12; H10; H10B; H10B80/00; H10W; H10W70/00; H10W70/40; H10W70/453; H10W90/00; H05K2201/00; H05K2201/10; H05K2201/10431; H05K2201/10507; H05K2201/10515; H05K2201/10613; H05K2201/10621; H05K2201/10681; H05K2203/00; H05K2203/15; H05K2203/1572; H05K3/00; H05K3/30; H05K3/32; H05K3/34; H05K3/3447; H05K3/36; H05K3/368; H10W70/60; H10W72/00; H10W72/01; H10W72/012; H10W72/01251; H10W72/01255; H10W72/60; H10W72/834; H10W90/20; H10W90/22; H10W90/291; H10W90/701; H10W90/721; H10W90/724
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
175 words
A semiconductor integrated circuit memory device comprising: (a) first and second semiconductor chips each of which has a substantially rectangular flat shape and has first and second principal surfaces; (b) a number of bump electrode pads provided near a pair of opposing sides of said first principal surfaces of each of said semiconductor chips; (c) a number of leads each of which is made of metal sheet, each said lead connected with the corresponding bump electrode pads of each chip; (d) a module base plate; (e) an insulating member coated between said second principal surface of said first chip and said first principal surface of said second chip; (f) a plurality of connection terminals formed on said module base plate, said plurality of terminals are connected with said number of leads; and wherein the second semiconductor chip is stacked over the first semiconductor chip, and wherein the number of connection terminals is greater than the number of bump electrodes in one chip, and smaller than the total amount of bump electrodes of said semiconductor chips.
Claim 2
Dependent Claim
175 words
A semiconductor integrated circuit memory device comprising: (a) first and second semiconductor chips each of which has a substantially rectangular flat shape and has first and second principal surfaces; (b) a number of bump electrode pads provided near a pair of opposing sides of said first principal surfaces of each of said semiconductor chips; (c) a number of leads each of which is made of metal sheet, each said lead connected with the corresponding bump electrode pads of each chip; (d) a module base plate; (e) an insulating member coated between said second principal surface of said first chip and said first principal surface of said second chip; (f) a plurality of connection terminals formed on said module base plate, said plurality of terminals are connected with said number of leads; and wherein the second semiconductor chip is stacked over the first semiconductor chip, and wherein the number of connection terminals is greater than the number of bump electrodes in one chip, and smaller than the total amount of bump electrodes of said semiconductor chips.
Claim 3
Dependent Claim
210 words
A semiconductor integrated circuit memory device comprising: (a) first and second semiconductor chips each of which has a substantially rectangular flat shape and has first and second principal surfaces; (b) a number of bump electrode pads provided near a pair of opposing sides of said first principal surfaces of each of said semiconductor chips; (c) a number of leads each of which is made of metal sheet, each said lead connected with the corresponding bump electrode pads of each chip; (d) a module base plate; (e) an insulating member coated between said first principal surface of said first chip and said second principal surface of said second chip; wherein the second semiconductor chip is stacked over the first semiconductor chip, and each said bump electrode on said first chip and at least one bump electrode on said second chip is connected by at least one said lead to said base plate, and each said bump electrode on said second chip, with the exception of said at least one bump electrode connected to said base plate, is connected by one said metal sheet lead to the lead of said first chip that is directly beneath said bump electrode, and said connection being above the principal surface of said module base plate.
Claim 4
Dependent Claim
210 words
A semiconductor integrated circuit memory device comprising: (a) first and second semiconductor chips each of which has a substantially rectangular flat shape and has first and second principal surfaces; (b) a number of bump electrode pads provided near a pair of opposing sides of said first principal surfaces of each of said semiconductor chips; (c) a number of leads each of which is made of metal sheet, each said lead connected with the corresponding bump electrode pads of each chip; (d) a module base plate; (e) an insulating member coated between said first principal surface of said first chip and said second principal surface of said second chip; wherein the second semiconductor chip is stacked over the first semiconductor chip, and each said bump electrode on said first chip and at least one bump electrode on said second chip is connected by at least one said lead to said base plate, and each said bump electrode on said second chip, with the exception of said at least one bump electrode connected to said base plate, is connected by one said metal sheet lead to the lead of said first chip that is directly beneath said bump electrode, and said connection being above the principal surface of said module base plate.
Claim 5
Dependent Claim
26 words
A semiconductor integrated circuit memory device according to claim 1 wherein first and second stacked arrays are mounted on front and rear surfaces of base plate.
Claim 6
Dependent Claim
218 words
A semiconductor integrated circuit memory device comprising: (a) first and second semiconductor chips each of which has a substantially rectangular flat shape and has first and second principal surfaces; (b) a plurality of bump electrode pads disposed on one of said first and second principal surfaces near a pair of opposing sides of said principal surfaces of each of said semiconductor chips; (c) a plurality of leads, each of which is made of metal sheet, each said lead connected with the corresponding bump electrode pads of each chip; (d) a module base plate; (e) an insulating member coated between said second principal surface of said first chip and said first principal surface of said second chip; wherein at least one of said bump electrodes on said first chip is arranged so as to mirror image location with respect to a corresponding one of said bump electrodes on said second chip, and said second chip is stacked above said first chip, wherein bump electrodes on said first chip which contact corresponding bump electrodes on said second chip are connected by one said lead to the module base plate, and bump electrodes on said chips which do not contact bump electrodes on the opposing chip in said stacked array are connected by one said lead to the module base plate.
Claim 7
Dependent Claim
218 words
A semiconductor integrated circuit memory device comprising: (a) first and second semiconductor chips each of which has a substantially rectangular flat shape and has first and second principal surfaces; (b) a plurality of bump electrode pads disposed on one of said first and second principal surfaces near a pair of opposing sides of said principal surfaces of each of said semiconductor chips; (c) a plurality of leads, each of which is made of metal sheet, each said lead connected with the corresponding bump electrode pads of each chip; (d) a module base plate; (e) an insulating member coated between said second principal surface of said first chip and said first principal surface of said second chip; wherein at least one of said bump electrodes on said first chip is arranged so as to mirror image location with respect to a corresponding one of said bump electrodes on said second chip, and said second chip is stacked above said first chip, wherein bump electrodes on said first chip which contact corresponding bump electrodes on said second chip are connected by one said lead to the module base plate, and bump electrodes on said chips which do not contact bump electrodes on the opposing chip in said stacked array are connected by one said lead to the module base plate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-31 | 1994-07-02 | 1995-01-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-31 | 1998-07-02 | 1999-01-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-31 | 2002-07-02 | 2003-01-01 | $7700.00 | Window Closed / Lapsed |