Patent US3228164A successfully refreshed from Google Patents.
US3838501A
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US
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Method in microcircuit package assembly providing nonabrasive, electrically passive edges on integrated circuit chips
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1973-02-09
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Granted: 1974-10-01
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Expires: 1993-02-09
Abstract
Abstract A channel is formed in the kerf area of an integrated circuit wafer prior to forming a passivating or protective layer of material on the surface of the wafer. The passivated channel, after separation of the wafer into chips, forms conditioned edges which prevent shorting of interconnecting leads.
Inventors
- 👤 C Umbaugh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:56
CPC Classifications
H; H10; H10W; H10W99/00; H10D; H10D62/00; H10D62/10; H10D62/117; H10D99/00; H10P; H10P54/00; H10W72/00; H10W72/50; H10W72/581; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49121
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
191 words
An improved method in microelectronic circuit fabrication and assembly providing nonabrasive electrically passive edges on face-up mounted chips, the improvement comprising the steps of: forming a channel in a kerf area on an active surface of a wafer of semiconductor material; depositing a layer of passivating material on the active surface of the wafer, the layer covering the channel formed in the previous step; separating the wafer into individual chips along the centerline of the channel, the separating kerf having a width substantially less than the width of the channel, the remaining portions of the bisected channel forming chamfered, passivated edges on each of the separated chips; attaching a lead to a contact pad of one of the individual chips, the lead being free cantilevered over the remaining channel portion of the chip; attaching the one chip face-up to one surface of a planiform insulator, the lead aligned over an external circuit formed on the one surface; and forcing the cantilevered lead toward the external circuit to make electrical contact therewith, the chamfered passivated edge reducing the probability of electrical shorts between the lead and the semiconductor material of the chip.
Claim 2
Dependent Claim
191 words
An improved method in microelectronic circuit fabrication and assembly providing nonabrasive electrically passive edges on face-up mounted chips, the improvement comprising the steps of: forming a channel in a kerf area on an active surface of a wafer of semiconductor material; depositing a layer of passivating material on the active surface of the wafer, the layer covering the channel formed in the previous step; separating the wafer into individual chips along the centerline of the channel, the separating kerf having a width substantially less than the width of the channel, the remaining portions of the bisected channel forming chamfered, passivated edges on each of the separated chips; attaching a lead to a contact pad of one of the individual chips, the lead being free cantilevered over the remaining channel portion of the chip; attaching the one chip face-up to one surface of a planiform insulator, the lead aligned over an external circuit formed on the one surface; and forcing the cantilevered lead toward the external circuit to make electrical contact therewith, the chamfered passivated edge reducing the probability of electrical shorts between the lead and the semiconductor material of the chip.
Claim 3
Dependent Claim
184 words
An improved method in microcircuit fabrication and assembly providing nonabrasive electrically passive edges on face-up mounted chips, the improvement comprising the steps of: forming a channel in a kerf area on an active surface of a wafer of semiconductor material; depositing a layer of passivating material on the surface of the wafer, the layer covering the channel formed in the previous step; attaching a lead to a contact pad on the active surface, the lead freely extending in a cantilevered fashion over the channel; separating the wafer into individual chips along the centerline of the channel, the separating kerf having a width substantially less than the width of the channel, the remaining portions of the bisected channel forming chamfered, passivated edges on the chips; attaching the chip having the lead face-up to one surface of a planiform insulator, the lead aligned over an external circuit formed on the one surface; and forcing the cantilevered lead toward the external circuit to make electrical contact therewith, the chamfered passivated edge reducing the probability of electrical shorts between the lead and the semiconductor material of the chip.
Claim 4
Dependent Claim
184 words
An improved method in microcircuit fabrication and assembly providing nonabrasive electrically passive edges on face-up mounted chips, the improvement comprising the steps of: forming a channel in a kerf area on an active surface of a wafer of semiconductor material; depositing a layer of passivating material on the surface of the wafer, the layer covering the channel formed in the previous step; attaching a lead to a contact pad on the active surface, the lead freely extending in a cantilevered fashion over the channel; separating the wafer into individual chips along the centerline of the channel, the separating kerf having a width substantially less than the width of the channel, the remaining portions of the bisected channel forming chamfered, passivated edges on the chips; attaching the chip having the lead face-up to one surface of a planiform insulator, the lead aligned over an external circuit formed on the one surface; and forcing the cantilevered lead toward the external circuit to make electrical contact therewith, the chamfered passivated edge reducing the probability of electrical shorts between the lead and the semiconductor material of the chip.
Claim 5
Dependent Claim
235 words
An improved method in microcircuit fabrication and assembly providing nonabrasive electrically passive edges on face-up mounted integrated circuit dice, the improvement comprising the steps of: forming a channel in a kerf area on an active surface of a wafer of semiconductor material, after circuits have been formed on the active surface of the wafer but prior to final wafer passivation; depositing a layer of passivating material on the active surface of the wafer, the layer covering the channel formed in the previous step; dicing the wafer along the centerline of the channel, the separating kerf having a width substantially less than the width of the channel, the remaining portions of the bisected channel forming chamfered, passivated edges on each of the dice; attaching a lead to a contact pad of at least one of the circuits, the lead freely extending in cantilevered fashion over the remaining channel portion of the die; attaching the die having the lead attached thereto to one surface of a planar substrate having an external circuit formed thereon, the plane of the lead separated from the plane of the external circuit by the thickness of the die, the lead aligned over the external circuit; and forcing the extended portion of the lead toward the external circuit to make electrical contact therewith, the chamfered passivated edge reducing the probability of electrical shorts between the lead and the semiconductor material of the die.
Claim 6
Dependent Claim
235 words
An improved method in microcircuit fabrication and assembly providing nonabrasive electrically passive edges on face-up mounted integrated circuit dice, the improvement comprising the steps of: forming a channel in a kerf area on an active surface of a wafer of semiconductor material, after circuits have been formed on the active surface of the wafer but prior to final wafer passivation; depositing a layer of passivating material on the active surface of the wafer, the layer covering the channel formed in the previous step; dicing the wafer along the centerline of the channel, the separating kerf having a width substantially less than the width of the channel, the remaining portions of the bisected channel forming chamfered, passivated edges on each of the dice; attaching a lead to a contact pad of at least one of the circuits, the lead freely extending in cantilevered fashion over the remaining channel portion of the die; attaching the die having the lead attached thereto to one surface of a planar substrate having an external circuit formed thereon, the plane of the lead separated from the plane of the external circuit by the thickness of the die, the lead aligned over the external circuit; and forcing the extended portion of the lead toward the external circuit to make electrical contact therewith, the chamfered passivated edge reducing the probability of electrical shorts between the lead and the semiconductor material of the die.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-09-30 | 1978-04-01 | 1978-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-09-30 | 1982-04-01 | 1982-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-09-30 | 1986-04-01 | 1986-10-01 | $7700.00 | Window Closed / Lapsed |