US5646067A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of bonding wafers having vias including conductive material
Assignee: Intersil Americas LLC
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Filing: 1995-06-05
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Granted: 1997-07-08
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Expires: 2015-06-05
Abstract
Abstract A surface mountable integrated circuit and a method of manufacture are disclosed. A wafer 110 has a die with an integrated circuit 119 in one surface of the wafer. A via 130 extends to the opposite surface. The via has a sidewall oxide 131 and is filled with a conductive material such as metal or doped polysilicon. The metal may comprise a barrier layer and an adhesion layer. The second end of the via can be fashioned as a prong 233 or a receptacle 430. Dies with vias can be stacked on top of each other or surface mounted to printed circuit boards or other substrate.
Inventors
- 👤 Stephen Joseph Gaul
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:31
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/021; H10W20/023; H10W20/0234; H10W20/0238; H10W20/0245; H10W20/0249; H10W20/0257; H10W20/20; H10W20/211; H10W20/216; H10W90/00; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W70/654; H10W70/655; H10W70/656; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/07254; H10W72/20; H10W72/241; H10W72/242; H10W72/244; H10W72/50; H10W72/551; H10W72/552; H10W72/834; H10W90/20; H10W90/288; H10W90/297; H10W90/701; H10W90/721; H10W90/722; H10W90/751; H10W90/754; Y; Y10; Y10S; Y10S148/00; Y10S148/012; Y10S148/135
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
150 words
A method for fabricating surface mountable integrated circuits comprising the steps of: providing a device wafer of monocrystalline silicon material with first and second surfaces and with integrated circuits formed on the first surface of said device wafer; forming an oxide layer between the second surface of the device wafer and a handle wafer, said oxide layer bonding the handle wafer to the device wafer for supporting the device wafer; forming a via in the device wafer, said via comprising a first open end on the first surface of the device wafer, an elongated passage extending from said open end a controlled depth into the handle wafer and terminating at a second end closed by said handle wafer; depositing a conductive material in the via over the elongated surface and the closed end of the via; removing the handle wafer to expose the conductive material coated on the via surface.
Claim 2
Independent Claim
150 words
A method for fabricating surface mountable integrated circuits comprising the steps of: providing a device wafer of monocrystalline silicon material with first and second surfaces and with integrated circuits formed on the first surface of said device wafer; forming an oxide layer between the second surface of the device wafer and a handle wafer, said oxide layer bonding the handle wafer to the device wafer for supporting the device wafer; forming a via in the device wafer, said via comprising a first open end on the first surface of the device wafer, an elongated passage extending from said open end a controlled depth into the handle wafer and terminating at a second end closed by said handle wafer; depositing a conductive material in the via over the elongated surface and the closed end of the via; removing the handle wafer to expose the conductive material coated on the via surface.
Claim 3
Dependent Claim
40 words
The method of claim 1 wherein the handle wafer is removed to expose a surface of said oxide bonding layer and the conductive material of the second end of the via extends beyond the surface of the oxide bonding layer.
Claim 4
Dependent Claim
24 words
The method of claim 1 wherein the conductive material deposited over the surface of the via comprises a metal deposited on the via surface.
Claim 5
Dependent Claim
29 words
The method of claim 3 wherein the metal comprises a first layer of a barrier metal and a second layer of an adhesion metal deposited on the barrier metal.
Claim 6
Dependent Claim
45 words
The method of claim 4 wherein the barrier metal is one metal selected from the group consisting of titanium nitride, copper, lead, platinum, and nickel and the adhesion metal is another metal selected from the group consisting of titanium nitride, chromium, titanium, and titanium tungsten.
Claim 7
Dependent Claim
15 words
The method of claim 4 further comprising the step of filling the via with polysilicon.
Claim 8
Dependent Claim
20 words
The method of claim 6 further comprising the step of planarizing the layers of adhesion metal, barrier metal and polysilicon.
Claim 9
Dependent Claim
58 words
The method of claim 1 wherein the step of depositing a conductive material comprises the steps of depositing a layer of titanium nitride, depositing a layer of tungsten on the layer of titanium nitride, and depositing a layer of polysilicon over the titanium nitride to fill the via, and planarizing the layers of titanium nitride, tungsten, and polysilicon.
Claim 10
Dependent Claim
27 words
The method of claim 1 further comprising the step of dielectrically isolating the surface of the via from the monocrystalline silicon material before depositing the conductive material.
Claim 11
Dependent Claim
20 words
The method of claim 9 further comprising the step of depositing a dielectric material on the surface of the via.
Claim 12
Dependent Claim
23 words
The method of claim 10 wherein the deposited dielectric is one selected from the group consisting of silicon dioxide, silicon nitride, and diamond.
Claim 13
Dependent Claim
20 words
The method of claim 9 further comprising the step of forming a dielectric layer on the surface of the via.
Claim 14
Dependent Claim
26 words
The method of claim 12 wherein the monocrystalline silicon material in the via is oxidized to form a dielectric layer on the surface of the via.
Claim 15
Dependent Claim
18 words
The method of claim 1 wherein the via is filled to the first surface with a conductive material.
Claim 16
Dependent Claim
67 words
The method of claim 1 comprising the further steps of: filling the via with photoresist; developing a portion of the photoresist extending a controlled depth from the first surface of the wafer; removing the developed portion of resist from the end of the via between the first surface and the controlled depth; filling the via with a conductive material between the first surface and the controlled depth.
Claim 17
Dependent Claim
37 words
The method of claim 1 comprising the further steps of: depositing a metal contact layer on the surface of the wafer; patterning the metal contact layer to provide conductive paths between the integrated circuit and the vias.
Claim 18
Dependent Claim
15 words
The method of claim 1 wherein the exposed conductive material of the via is silicided.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-07 | 2001-01-06 | 2001-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-07 | 2005-01-06 | 2005-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-07 | 2009-01-06 | 2009-07-08 | $7700.00 | Window Closed / Lapsed |