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US5024966A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of forming a silicon-based semiconductor optical device mount

Assignee: Nokia Bell Labs
•
Filing: 1990-04-16
•
Granted: 1991-06-18
•
Expires: 2010-04-16
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Abstract

Abstract A silicon-based laser mounting structure is disclosed which provides improved interconnection between a semiconductor optical device, such as a laser, and an external high frequency modulation current source, by reducing the presence of parasitic inductive elements in the interconnecting network. The structure includes a stripline transmission path formed by depositing metal conductive strips on the top and bottom surfaces of a silicon substrate. The conductive strips are coupled at one end to the external modulation current source. A thin film resistor is deposited between the second end of the top conductive strip and the semiconductor optical device. This thin film resistor is utilized to provide impedance matching between the optical device and the stripline. That is, for a laser with an impedance Z L , and a stripline designed to have an impedance Z S , the resistance R is chosen such that R+Z L =Z S . Utilizing silicon processing techniques, the thin film resistor may be placed adjacent to the laser, reducing the parasitics associated with their interconnection. A conductive via is formed through the substrate to provide a top-side bonding location for connecting the optical device to the bottom metal conductor by providing the top-side site, the parasitic inductance associated with this interconnection is considerably reduced.

Inventors

  • 👤 Norman R. Dietrich
  • 👤 Ralph S. Moyer
  • 👤 Yiu-Huen Wong

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 22:15
CPC Classifications
H; H01; H01S; H01S5/00; H01S5/02; H01S5/022; H01S5/0233; H01S5/02345; H01S5/04; H01S5/042; H01S5/0427; H01S5/06; H01S5/062; H01S5/06226; H10; H10W; H10W72/00; H10W72/50; H10W72/531; H10W72/536; Y; Y10; Y10S; Y10S148/00; Y10S148/099; Y10S148/168; Y10S438/00; Y10S438/928

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 145 words
A method of forming a silicon-based stripline for providing an interconnection between a semiconductor optical device and a high frequency modulation signal source, said method comprising the steps of: (a) providing a silicon substrate including first and second opposing major surfaces; (b) depositing a thin film resistor on said first major surface of said substrate; (c) forming a via through said silicon substrate at a spaced-apart location from said thin film resistor and; (d) metallizing longitudinal portions of said first and second major surfaces of said substrate, as well as the via, the first longitudinal portion being of a predetermined width w, the combination of said first and second metallized longitudinal portions with said substrate thus forming a stripline transmission path with a characteristic impedance Z s , and the via being utilized to provide electrical connection between the second metallization and the semiconductor device.
Claim 2
Independent Claim 145 words
A method of forming a silicon-based stripline for providing an interconnection between a semiconductor optical device and a high frequency modulation signal source, said method comprising the steps of: (a) providing a silicon substrate including first and second opposing major surfaces; (b) depositing a thin film resistor on said first major surface of said substrate; (c) forming a via through said silicon substrate at a spaced-apart location from said thin film resistor and; (d) metallizing longitudinal portions of said first and second major surfaces of said substrate, as well as the via, the first longitudinal portion being of a predetermined width w, the combination of said first and second metallized longitudinal portions with said substrate thus forming a stripline transmission path with a characteristic impedance Z s , and the via being utilized to provide electrical connection between the second metallization and the semiconductor device.
Claim 3
Dependent Claim 20 words
The method according to claim 1 wherein in performing step (b), tantalum nitride is deposited as the thin film resistor.
Claim 4
Dependent Claim 19 words
The method according to claim 2 wherein in performing step (b), a plasma-enhanced chemical vapor deposition technique is utilized.
Claim 5
Dependent Claim 22 words
The method according to claim 1 wherein in performing step (a), a (100) silicon substrate with a <110> lithographic orientation is provided.
Claim 6
Dependent Claim 34 words
The method according to claim 4 wherein in performing step (c), the etchant ethylenediamine pyrocatechol (EDP) is utilized to form an inverted V-shaped via with respect to the first major surface of the substrate.
Claim 7
Dependent Claim 27 words
The method according to claim 1 wherein in performing step (d), the metallizations comprises a tri-level metallization of titanium, platinum and gold, deposited sequentially on said substrate.
Claim 8
Dependent Claim 20 words
The method according to claim 1 wherein in performing step (d), a sputtering operation is used to deposit the metallizations.

References Cited (Backward Citations)

US3343256A Cited
US3757259A Cited
US4035748A Cited
US4097891A Cited
US4301429A Cited
US4418466A Cited
US4379273A Cited
US4485361A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-06-17 1994-12-17 1995-06-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-06-17 1998-12-17 1999-06-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-06-17 2002-12-17 2003-06-18 $7700.00 Window Closed / Lapsed

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