US5268326A
Expired / Lapsed
US
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Method of making dielectric and conductive isolated island
Assignee: Motorola Solutions Inc
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Filing: 1992-09-28
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Granted: 1993-12-07
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Expires: 2012-09-28
Abstract
Abstract A dielectric and conductive isolated island is fabricated by providing an active wafer having a first and a second major surface, a doped region extending from the first surface, and a trench formed at the first surface. A conductive layer is formed on the first surface and in the trench. A planarizable layer comprised of a dielectric layer is then formed on the conductive layer. A handle wafer is bonded to the planarizable layer. The active wafer and the handle wafer are heated so that the doped region diffuses along the conductive layer to form an equalized concentration of dopant along the conductive layer which diffuses into the active wafer to form the doped region adjacent all of the conductive layer. A portion of the second surface of the active wafer is then removed so that at least a portion of the dielectric layer of the planarizable layer is exposed.
Inventors
- 👤 Israel A. Lesk
- 👤 Frank S. d'Aragona
- 👤 Francine Y. Robb
- 👤 Raymond C. Wells
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 02:12
CPC Classifications
H; H10; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10P90/1914; H10W10/041; H10W10/40; Y; Y10; Y10S; Y10S148/00; Y10S148/012; Y10S148/135; Y10S438/00; Y10S438/928
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
216 words
A method of forming a dielectric and conductive isolated island, comprising the steps of: providing a semiconductor wafer having a first surface and a second surface; forming a doped region extending into the semiconductor wafer from the first surface; forming a trench extending into the semiconductor wafer from the first surface farther than the doped region to form an island; forming a first conductive layer on the first surface of the semiconductor wafer and in the trench; forming a planarizable layer comprised of a dielectric layer on the first conductive layer and in the trench so that the trench is at least filled by the planarizable layer; planarizing the planarizable layer; providing a handle wafer having a first surface and a second surface; bonding the handle wafer and the semiconductor wafer together so that the first surface of the handle wafer and the planarizable layer are joined; diffusing the doped region farther into the semiconductor wafer; and removing a portion of the second surface of the semiconductor wafer so that at least a portion of the planarizable layer is exposed to provide the island of the semiconductor wafer surrounded by the conductive layer and the dielectric layer of the planarizable layer, wherein the doped region is present at at least a portion of the second surface.
Claim 2
Independent Claim
216 words
A method of forming a dielectric and conductive isolated island, comprising the steps of: providing a semiconductor wafer having a first surface and a second surface; forming a doped region extending into the semiconductor wafer from the first surface; forming a trench extending into the semiconductor wafer from the first surface farther than the doped region to form an island; forming a first conductive layer on the first surface of the semiconductor wafer and in the trench; forming a planarizable layer comprised of a dielectric layer on the first conductive layer and in the trench so that the trench is at least filled by the planarizable layer; planarizing the planarizable layer; providing a handle wafer having a first surface and a second surface; bonding the handle wafer and the semiconductor wafer together so that the first surface of the handle wafer and the planarizable layer are joined; diffusing the doped region farther into the semiconductor wafer; and removing a portion of the second surface of the semiconductor wafer so that at least a portion of the planarizable layer is exposed to provide the island of the semiconductor wafer surrounded by the conductive layer and the dielectric layer of the planarizable layer, wherein the doped region is present at at least a portion of the second surface.
Claim 3
Dependent Claim
22 words
The method of claim 1 wherein the step of forming the first conductive layer comprises forming a silicon rich conductive silicide layer.
Claim 4
Dependent Claim
23 words
The method of claim 1 further wherein the step of forming the first conductive layer comprises forming a first silicon rich tungsten silicide.
Claim 5
Dependent Claim
24 words
The method of claim 1 further wherein the step of forming the doped region comprises co-ion implanting arsenic and phosphorus into the semiconductor wafer.
Claim 6
Dependent Claim
20 words
The method of claim 1 further wherein the step of forming the first conductive layer comprises forming a titanium nitride.
Claim 7
Dependent Claim
37 words
The method of claim 1 wherein the step of providing the handle wafer comprises providing the handle wafer having a second conductive layer on the first surface and an amorphous semiconductor layer on the second conductive layer.
Claim 8
Dependent Claim
39 words
The method of claim 1 wherein the step of bonding the semiconductor wafer to the handle wafer comprises heating the semiconductor wafer and the handle wafer at a temperature of approximately 1150°-1250° C. for approximately 50-70 minutes in steam.
Claim 9
Dependent Claim
35 words
The method of claim 1 wherein the step of providing the semiconductor wafer comprises providing the semiconductor wafer having a denuded zone extending into the semiconductor wafer from the first surface farther than the trench.
Claim 10
Dependent Claim
74 words
The method of claim 2 wherein the step of forming the planarizable layer comprises the steps of: forming the dielectric layer of the planarizable layer on the silicon rich conductive silicide layer by heating the semiconductor wafer such that silicon diffuses out of the silicon rich conductive silicide layer, thus converting the silicon rich conductive layer to a conductive silicide layer; and forming a planarizable portion of the planarizable layer on the dielectric layer.
Claim 11
Independent Claim
287 words
A method of forming a dielectric and conductive isolated island, comprising the steps of: providing an semiconductor wafer having a first surface and a second surface; forming a doped region extending into the semiconductor wafer from the fist surface by introducing a dopant into the semiconductor wafer; forming a trench extending into the semiconductor wafer from the first surface farther than the doped region to form an island; forming a first silicon rich conductive silicide layer on the first surface of the semiconductor wafer and in the trench; converting the first silicon rich conductive silicide layer to a first conductive silicide layer so that a dielectric layer is formed on the first conductive silicide layer; forming a planarizable layer on the dielectric layer and in the trench so that the trench is at least filled by the planarizable layer; planarizing the planarizable layer; providing a handle wafer having a first surface and a second surface; bonding the handle wafer and the semiconductor wafer together so that the first surface of the handle wafer and the planarizable layer are joined; diffusing the doped region so that the dopant from the doped region diffuses along the conductive silicide layer to form an equalized concentration of dopant along the conductive silicide layer which diffuses into the semiconductor wafer to form the doped region adjacent all of the conductive silicide layer; and removing a portion of the second surface of the semiconductor wafer so that at least a portion of the planarizable layer is exposed to provide the island of the semiconductor wafer surrounded by the conductive layer and the dielectric layer of the planarizable layer, wherein the doped region is present at at least a portion of the second surface.
Claim 12
Independent Claim
287 words
A method of forming a dielectric and conductive isolated island, comprising the steps of: providing an semiconductor wafer having a first surface and a second surface; forming a doped region extending into the semiconductor wafer from the fist surface by introducing a dopant into the semiconductor wafer; forming a trench extending into the semiconductor wafer from the first surface farther than the doped region to form an island; forming a first silicon rich conductive silicide layer on the first surface of the semiconductor wafer and in the trench; converting the first silicon rich conductive silicide layer to a first conductive silicide layer so that a dielectric layer is formed on the first conductive silicide layer; forming a planarizable layer on the dielectric layer and in the trench so that the trench is at least filled by the planarizable layer; planarizing the planarizable layer; providing a handle wafer having a first surface and a second surface; bonding the handle wafer and the semiconductor wafer together so that the first surface of the handle wafer and the planarizable layer are joined; diffusing the doped region so that the dopant from the doped region diffuses along the conductive silicide layer to form an equalized concentration of dopant along the conductive silicide layer which diffuses into the semiconductor wafer to form the doped region adjacent all of the conductive silicide layer; and removing a portion of the second surface of the semiconductor wafer so that at least a portion of the planarizable layer is exposed to provide the island of the semiconductor wafer surrounded by the conductive layer and the dielectric layer of the planarizable layer, wherein the doped region is present at at least a portion of the second surface.
Claim 13
Dependent Claim
26 words
The method of claim 10 further wherein the step of forming the first silicon rich conductive silicide layer comprises forming a first silicon rich tungsten silicide.
Claim 14
Dependent Claim
24 words
The method of claim 10 further wherein the step of forming the doped region comprises co-ion implanting arsenic and phosphorus into the semiconductor wafer.
Claim 15
Dependent Claim
43 words
The method of claim 10 wherein the step of providing the handle wafer comprises providing the handle wafer having a second silicon rich conductive silicide layer on the first surface and an amorphous semiconductor layer on the second silicon rich conductive silicide layer.
Claim 16
Dependent Claim
58 words
The method of claim 13 wherein the step of bonding the semiconductor wafer and the handle wafer comprises the silicon rich conductive silicide layer expelling excess silicon to convert the silicon rich conductive silicide layer to a conductive silicide layer, wherein the excess silicon diffuses to form a void-free bond between the semiconductor wafer and the handle wafer.
Claim 17
Dependent Claim
39 words
The method of claim 10 wherein the step of bonding the semiconductor wafer to the handle wafer comprises heating the semiconductor wafer and the handle wafer at a temperature of approximately 1150°-1250° C. for approximately 50-70 minutes in steam.
Claim 18
Dependent Claim
35 words
The method of claim 10 wherein the step of providing the semiconductor wafer comprises providing the semiconductor wafer having a denuded zone extending into the semiconductor wafer from the first surface farther than the trench.
Claim 19
Dependent Claim
26 words
The method of claim 10 wherein the doped region extends at least from the first surface of the semiconductor wafer to the bottom of the trench.
Claim 20
Independent Claim
240 words
A method of forming a dielectric and conductive isolated island, comprising the steps of: providing a semiconductor wafer having a first surface and a second surface; forming a trench extending into the semiconductor wafer from the first surface, wherein the trench has a bottom; forming a doped region after the step of forming the trench, wherein the doped region extends into the semiconductor wafer from the first surface shallower than the bottom of the trench and extends into the semiconductor wafer from the trench; forming a first conductive layer on the first surface of the semiconductor wafer and in the trench; forming a planarizable layer comprised of a dielectric layer on the first conductive layer and in the trench so that the trench is at least filled by the planarizable layer; planarizing the planarizable layer; providing a handle wafer having a first surface and a second surface; bonding the handle wafer and the semiconductor wafer together so that the first surface of the handle wafer and the planarizable layer are joined; diffusing the doped region farther into the semiconductor wafer; and removing a portion of the second surface of the semiconductor wafer so that at least a portion of the planarizable layer is exposed to provide the island of the semiconductor wafer surrounded by the conductive layer and the dielectric layer of the planarizable layer, wherein the doped region is present at at least a portion of the second surface.
Claim 21
Independent Claim
240 words
A method of forming a dielectric and conductive isolated island, comprising the steps of: providing a semiconductor wafer having a first surface and a second surface; forming a trench extending into the semiconductor wafer from the first surface, wherein the trench has a bottom; forming a doped region after the step of forming the trench, wherein the doped region extends into the semiconductor wafer from the first surface shallower than the bottom of the trench and extends into the semiconductor wafer from the trench; forming a first conductive layer on the first surface of the semiconductor wafer and in the trench; forming a planarizable layer comprised of a dielectric layer on the first conductive layer and in the trench so that the trench is at least filled by the planarizable layer; planarizing the planarizable layer; providing a handle wafer having a first surface and a second surface; bonding the handle wafer and the semiconductor wafer together so that the first surface of the handle wafer and the planarizable layer are joined; diffusing the doped region farther into the semiconductor wafer; and removing a portion of the second surface of the semiconductor wafer so that at least a portion of the planarizable layer is exposed to provide the island of the semiconductor wafer surrounded by the conductive layer and the dielectric layer of the planarizable layer, wherein the doped region is present at at least a portion of the second surface.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-06 | 1997-06-07 | 1997-12-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-06 | 2001-06-07 | 2001-12-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-06 | 2005-06-07 | 2005-12-07 | $7700.00 | Window Closed / Lapsed |