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US5420064A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing a dielectric isolation substrate

Assignee: NEC Electronics Corp
•
Filing: 1994-09-22
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Granted: 1995-05-30
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Expires: 2014-09-22
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Abstract

Abstract According to this invention, there is provided a method of manufacturing a semiconductor device, including the steps of anisotropically etching a surface of an n-type monocrystalline silicon substrate having the (100) plane to form a V-shaped isolation groove having a depth d 1 , performing ion implantation and performing annealing and diffusion to a surface of the V-shaped isolation groove to form an n + -type buried layer, depositing a silicon dioxide film having a thickness d 2 on a surface of the n + -type buried layer, forming a polycrystalline silicon film on a surface of the silicon dioxide film, abrading and polishing the polycrystalline silicon film to have a thickness d 3 , adhering a monocrystalline silicon support substrate having a thickness d 4 to a polished surface of the polycrystalline silicon film at room temperature in the atmospheric air, abrading and polishing a lower surface of the n-type monocrystalline silicon substrate having the V-shaped isolation groove to expose the silicon dioxide film at a bottom portion of the V-shaped isolation groove on the lower surface and to form an island-like monocrystalline silicon film, wherein the thicknesses d 1 , d 2 , d 3 , and d 4 are set to be 50 to 60 μm, 1 to 3 μm, 0 to 30 μm, and 350 to 450 μm, respectively.

Inventors

  • 👤 Kensuke Okonogi
  • 👤 Tsukasa Ohoka

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 01:19
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/019; H10W10/10; Y; Y10; Y10S; Y10S148/00; Y10S148/012; Y10S148/135

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 216 words
A method of manufacturing a semiconductor device, comprising the steps of anisotropically etching a surface of an n-type monocrystalline silicon substrate having the (100) plane to form a V-shaped isolation groove having a depth d 1 , performing ion implantation and performing annealing and diffusion to a surface of said V-shaped isolation groove to form an n + -type buried layer, depositing a silicon dioxide film having a thickness d 2 on a surface of said n + -type buried layer, forming a polycrystalline silicon film on a surface of said silicon dioxide film, abrading and polishing said polycrystalline silicon film to have a thickness d 3 , adhering a monocrystalline silicon support substrate having a thickness d 4 to a polished surface of said polycrystalline silicon film at room temperature in the atmospheric air, abrading and polishing a lower surface of said n-type monocrystalline silicon substrate having said V-shaped isolation groove to expose said silicon dioxide film at a bottom portion of said V-shaped isolation groove on said lower surface and to form an island-like monocrystalline silicon film, wherein the thicknesses d 1 , d 2 , d 3 , and d 4 are set to be 50 to 60 μm, 1 to 3 μm, 0 to 30 μm, and 350 to 450 μm, respectively.
Claim 2
Independent Claim 216 words
A method of manufacturing a semiconductor device, comprising the steps of anisotropically etching a surface of an n-type monocrystalline silicon substrate having the (100) plane to form a V-shaped isolation groove having a depth d 1 , performing ion implantation and performing annealing and diffusion to a surface of said V-shaped isolation groove to form an n + -type buried layer, depositing a silicon dioxide film having a thickness d 2 on a surface of said n + -type buried layer, forming a polycrystalline silicon film on a surface of said silicon dioxide film, abrading and polishing said polycrystalline silicon film to have a thickness d 3 , adhering a monocrystalline silicon support substrate having a thickness d 4 to a polished surface of said polycrystalline silicon film at room temperature in the atmospheric air, abrading and polishing a lower surface of said n-type monocrystalline silicon substrate having said V-shaped isolation groove to expose said silicon dioxide film at a bottom portion of said V-shaped isolation groove on said lower surface and to form an island-like monocrystalline silicon film, wherein the thicknesses d 1 , d 2 , d 3 , and d 4 are set to be 50 to 60 μm, 1 to 3 μm, 0 to 30 μm, and 350 to 450 μm, respectively.
Claim 3
Dependent Claim 21 words
A method according to claim 1, wherein said polycrystalline silicon film is abraded and polished through a mechanical and chemical action.
Claim 4
Dependent Claim 55 words
A method according to claim 1, further comprising the step of performing annealing at a temperature of 1,100° C. in an N 2 gas atmosphere for 2 hours after said polycrystalline silicon film adheres to said monocrystalline silicon support substrate in the step of adhering said polycrystalline silicon film to said monocrystalline silicon support substrate.

References Cited (Backward Citations)

US4971925A Cited
JPS63202035A Cited
JPH03142854A Cited
US5081061A Cited
JPH03252154A Cited
US5183783A Cited
JPH0645429A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-05-29 1998-11-28 1999-05-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-05-29 2002-11-28 2003-05-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-05-29 2006-11-28 2007-05-30 $7700.00 Window Closed / Lapsed

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