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US5081061A Expired / Lapsed US ⏱️ 0.0 years remaining

Manufacturing ultra-thin dielectrically isolated wafers

Assignee: Intersil Corp
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Filing: 1991-03-07
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Granted: 1992-01-14
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Expires: 2011-03-07
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Abstract

Abstract A method including filling etched moats with a first dielectric layer and layer of polycrystalline material and planarizing. A second dielectric layer is formed on the first polycrystalline layer and a second layer of polycrystalline is formed on the second dielectric layer to form a handle. The starting material is then thinned to produce the dielectric isolated islands. Device forming steps are then performed. Finally, the handle is removed leaving a wafer having a thickness defined by the planarized surface of the first polycrystalline layer and the top surface of the first wafer.

Inventors

  • 👤 George V. Rouse
  • 👤 Paul S. Reinecke

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 09:08
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/019; H10W10/10; Y; Y10; Y10S; Y10S438/00; Y10S438/928; Y10S438/977

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 143 words
A method of fabricating dielectrically isolated, integrated circuits in ultra-thin wafers comprising: forming moats in a first surface of a first wafer having a first thickness; forming a first dielectric layer on said first surface and said moats; depositing a first polycrystalline layer on said first dielectric layer to fill said moats and planarizing to form a planar surface; depositing a second dielectric layer on said first polycrystalline layer; forming a handle on said second dielectric layer; thinning said first wafer from a second surface to form dielectrically isolated islands at a third surface of said first wafer; performing device formation steps on said third surface; and removing said handle down to said second dielectric layer to produce a wafer having a second thickness substantially defined by said planar surface of said first polycrystalline layer and said third surface of said first wafer.
Claim 2
Independent Claim 143 words
A method of fabricating dielectrically isolated, integrated circuits in ultra-thin wafers comprising: forming moats in a first surface of a first wafer having a first thickness; forming a first dielectric layer on said first surface and said moats; depositing a first polycrystalline layer on said first dielectric layer to fill said moats and planarizing to form a planar surface; depositing a second dielectric layer on said first polycrystalline layer; forming a handle on said second dielectric layer; thinning said first wafer from a second surface to form dielectrically isolated islands at a third surface of said first wafer; performing device formation steps on said third surface; and removing said handle down to said second dielectric layer to produce a wafer having a second thickness substantially defined by said planar surface of said first polycrystalline layer and said third surface of said first wafer.
Claim 3
Dependent Claim 27 words
A method according to claim 1, wherein said planarizing step and said thinning step are performed to form a wafer having said second thickness below 7 mils.
Claim 4
Dependent Claim 38 words
A method according to claim 1, wherein said removing step includes grinding said handle for a substantial portion of its thickness and etching the remaining portion of said handle using said second dielectric layer as a etching stop.
Claim 5
Dependent Claim 22 words
A method according to claim 1 wherein said handle is formed by depositing a second polycrystalline layer on said second dielectric layer.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-01-13 1995-07-15 1996-01-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-01-13 1999-07-15 2000-01-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-01-13 2003-07-15 2004-01-14 $7700.00 Window Closed / Lapsed

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