US5478781A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Polyimide-insulated cube package of stacked semiconductor device chips
Assignee: International Business Machines Corp
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Filing: 1994-10-27
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Granted: 1995-12-26
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Expires: 2014-10-27
Abstract
Abstract A cube package of stacked silicon semiconductor chips. To accommodate cube packaging, a metal transfer layer is added over the passivated chip face to bring all of the surface electrical contacts to a common chip edge. The metal transfer layer is insulated from the chip face and from the adjacent chip in the stack by polymer layers having a low dielectric constant, and a thermal expansion coefficient matching that of the stacked chips. An adhesive polymer layer is added to strengthen the bond between the first polymer layers and the adjacent chip in the stack, by deposition of the adhesive layer and partial cure at the wafer level, and then full cure when the chips are stacked together to form the cube.
Inventors
- 👤 Claude L. Bertin
- 👤 Paul A. Farrar, Sr.
- 👤 Wayne J. Howell
- 👤 Christopher P. Miller
- 👤 David J. Perlman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 06:14
CPC Classifications
H; H10; H10W; H10W90/00; H10W72/00; H10W72/834; H10W90/20; H10W90/297
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
146 words
A method for forming a semiconductor structure, comprising the steps of: forming a plurality of integrated circuit chips on an upper surface of a wafer, said wafer having a first coefficient of thermal expansion; forming a sandwich structure of a first insulation layer, a first layer of transfer metallurgy, and a second insulation layer on said wafer, said first and second layers of insulation having coefficients of thermal expansion that approximate that of said wafer and having dielectric constants no greater than approximately 4; applying a polymer adhesion material on top of said sandwich structure; drying said polymer adhesion material without full curing; dicing said wafer to separate said plurality of integrated circuit chips from one another; and stacking said plurality of integrated circuit chips together and bonding said stacked chips together by heating to a temperature sufficient to cause said polymer adhesion material to cure.
Claim 2
Independent Claim
146 words
A method for forming a semiconductor structure, comprising the steps of: forming a plurality of integrated circuit chips on an upper surface of a wafer, said wafer having a first coefficient of thermal expansion; forming a sandwich structure of a first insulation layer, a first layer of transfer metallurgy, and a second insulation layer on said wafer, said first and second layers of insulation having coefficients of thermal expansion that approximate that of said wafer and having dielectric constants no greater than approximately 4; applying a polymer adhesion material on top of said sandwich structure; drying said polymer adhesion material without full curing; dicing said wafer to separate said plurality of integrated circuit chips from one another; and stacking said plurality of integrated circuit chips together and bonding said stacked chips together by heating to a temperature sufficient to cause said polymer adhesion material to cure.
Claim 3
Dependent Claim
25 words
The method as recited in claim 1, wherein said first and second layers of insulation have a glass transition temperature of above approximately 150° C.
Claim 4
Dependent Claim
25 words
The method as recited in claim 1, wherein said first and second layers of insulation have a glass transition temperature of above approximately 350° C.
Claim 5
Dependent Claim
41 words
The method as recited in claim 1, wherein said first and second layers of insulation have a Young's Modulus of less than approximately 160 GPa measured along a first given plane of said first and second layers of insulation as formed.
Claim 6
Dependent Claim
52 words
The method as recited in claim 4, wherein said first and second layers of insulation have a Young's Modulus of less than approximately 10 GPa measured along a second given plane of said first and second layers of insulation as formed, said second given plane being orthogonal to said first given plane.
Claim 7
Dependent Claim
22 words
The method as recited in claim 1, wherein said first and second layers of insulation have the same coefficient of thermal expansion.
Claim 8
Dependent Claim
35 words
The method as recited in claim 6, wherein said coefficient of thermal expansion is less than approximately 50 ppm/°C. measured along a first given plane of said first and second layers of insulation as formed.
Claim 9
Dependent Claim
46 words
The method as recited in claim 7, wherein said coefficient of thermal expansion is less than approximately 200 ppm/°C. measured along a second given plane of said first and second layers of insulation as formed, said second given plane being orthogonal to said first given plane.
Claim 10
Dependent Claim
23 words
The method as recited in claim 1, wherein both of said first and second layers of insulation have dielectric constants of approximately 3.6.
Claim 11
Dependent Claim
17 words
The method as recited in claim 9, wherein said dielectric constants are substantially similar in all planes.
Claim 12
Dependent Claim
19 words
The method as recited in claim 10, wherein said first and second layers of insulation are comprised of BPDA-PDA.
Claim 13
Dependent Claim
51 words
The method as recited in claim 1, further comprising the steps of depositing a layer of polyimide on an exposed surface of the plurality of integrated circuit chips as bonded together; and depositing a layer of interconnect metallurgy that contacts said first layer of transfer metallurgy through said layer of polyimide.
Claim 14
Dependent Claim
16 words
The method as recited in claim 12, wherein said layer of polyimide is comprised of BPDA-PDA.
Claim 15
Dependent Claim
91 words
The method as recited in claim 1, wherein said step of forming said sandwich structure further comprises the steps of: depositing a first layer of polyimide on said wafer, and drying said first layer of polyimide without producing full imidization; depositing said layer of transfer metallurgy that extends through said first layer of polyimide to contact conductive portions of said integrated circuits on said plurality of integrated circuit chips; and depositing a second layer of polyimide on said wafer, and fully curing both of said first and second layers of polyimide.
Claim 16
Independent Claim
235 words
A method of forming a multi-chip integrated circuit structure, comprising the steps of: forming a plurality of integrated circuit chips on a wafer, said wafer having a first coefficient of thermal expansion, each of said plurality of integrated circuit chips having a first passivation layer thereon; forming an interconnection structure on said first passivation layer, comprising a first layer of metal disposed within a first polymer material, said first polymer material having a coefficient of thermal expansion that approximates that of said wafer and a dielectric constant that is less than approximately 4; forming an adhesive polymer layer on said interconnection structure, said adhesive polyimide layer being heated to stabilize without fully curing; dicing said plurality of integrated circuit chips from said wafer; bonding at least one of said plurality of integrated circuit chips to another one of said plurality of integrated circuit chips by bringing a surface of one of said plurality of integrated circuit chips into contact with a surface of another one of said plurality of integrated circuit chips having said layer of adhesive polymer layer thereon, and fully curing said adhesive polymer layer to form a unitized multi-chip body having a plurality of surfaces; depositing a second passivation layer on one of said plurality of surfaces of said unitized body; and forming a second layer of metal that extends through said second passivation layer to contact said first layer of metal.
Claim 17
Independent Claim
235 words
A method of forming a multi-chip integrated circuit structure, comprising the steps of: forming a plurality of integrated circuit chips on a wafer, said wafer having a first coefficient of thermal expansion, each of said plurality of integrated circuit chips having a first passivation layer thereon; forming an interconnection structure on said first passivation layer, comprising a first layer of metal disposed within a first polymer material, said first polymer material having a coefficient of thermal expansion that approximates that of said wafer and a dielectric constant that is less than approximately 4; forming an adhesive polymer layer on said interconnection structure, said adhesive polyimide layer being heated to stabilize without fully curing; dicing said plurality of integrated circuit chips from said wafer; bonding at least one of said plurality of integrated circuit chips to another one of said plurality of integrated circuit chips by bringing a surface of one of said plurality of integrated circuit chips into contact with a surface of another one of said plurality of integrated circuit chips having said layer of adhesive polymer layer thereon, and fully curing said adhesive polymer layer to form a unitized multi-chip body having a plurality of surfaces; depositing a second passivation layer on one of said plurality of surfaces of said unitized body; and forming a second layer of metal that extends through said second passivation layer to contact said first layer of metal.
Claim 18
Dependent Claim
44 words
The method of claim 15, wherein during said step of forming said plurality of integrated circuit chips on said wafer, said first passivation layer is etched to form an edge surface, such that during said dicing step said first passivation layer is not cut.
Claim 19
Dependent Claim
33 words
The method of claim 16, wherein said first polymer material is disposed over said edge surface of said first passivation layer, such that during said dicing step said first polymer material is cut.
Claim 20
Independent Claim
86 words
A method of bonding a first integrated circuit chip to a workpiece, of said first integrated circuit chip being diced from a wafer having a plurality of integrated circuit chip images on a first surface thereon including said first integrated circuit chip image, comprising the steps of depositing a polymer layer on a first surface of said wafer; drying said polymer layer; dicing said wafer; bringing said polymer layer on said first integrated circuit chip into contact with said workpiece; and fully curing said polymer layer.
Claim 21
Independent Claim
86 words
A method of bonding a first integrated circuit chip to a workpiece, of said first integrated circuit chip being diced from a wafer having a plurality of integrated circuit chip images on a first surface thereon including said first integrated circuit chip image, comprising the steps of depositing a polymer layer on a first surface of said wafer; drying said polymer layer; dicing said wafer; bringing said polymer layer on said first integrated circuit chip into contact with said workpiece; and fully curing said polymer layer.
Claim 22
Dependent Claim
38 words
The method of claim 18, further comprising the step of: prior to said step of depositing said polymer adhesive layer, thinning said wafer by removing a portion of a second surface of said wafer opposite said first surface.
Claim 23
Dependent Claim
38 words
The method of claim 18, further comprising the steps of: prior to said step of dicing said wafer, depositing a protective layer on said polymer layer; and after said step of dicing said wafer, removing said protective layer.
Claim 24
Dependent Claim
11 words
The method of claim 20, wherein said protective layer comprises photoresist.
Claim 25
Dependent Claim
25 words
The method of claim 18, further comprising the step of, after said step of dicing said wafer, removing a surface portion of said polymer layer.
Claim 26
Dependent Claim
57 words
The method of claim 18, further comprising the steps of: after said step of fully curing said polymer layer, bonding the first integrated circuit chip and said workpiece to a carrier, said carrier being comprised of a first material, said polymer material having a coefficient of thermal expansion that is similar to that of said first material.
Claim 27
Dependent Claim
15 words
The method of claim 23, wherein said first material is comprised of ceramic or glass.
Claim 28
Independent Claim
141 words
A method for forming a semiconductor structure comprising the steps of: a) forming a plurality of integrated circuit chips on a wafer, each of said plurality of integrated circuit chips having a first passivation layer thereon; b) forming a sandwich structure on said first passivation layer, said structure comprising a first polymeric insulation layer, a first rerouting metal layer and a second polymeric insulation layer; c) dicing said plurality of integrated circuit chips from said wafer; d) bonding at least one of said plurality of integrated circuit chips to another chip to form a unitized multi-chip body having a plurality of surfaces; e) depositing a second passivation layer on one of said plurality of surfaces of said unitized body; and f) forming a second layer of metal that extends through said second passivation layer to contact said first rerouting metal layer.
Claim 29
Independent Claim
141 words
A method for forming a semiconductor structure comprising the steps of: a) forming a plurality of integrated circuit chips on a wafer, each of said plurality of integrated circuit chips having a first passivation layer thereon; b) forming a sandwich structure on said first passivation layer, said structure comprising a first polymeric insulation layer, a first rerouting metal layer and a second polymeric insulation layer; c) dicing said plurality of integrated circuit chips from said wafer; d) bonding at least one of said plurality of integrated circuit chips to another chip to form a unitized multi-chip body having a plurality of surfaces; e) depositing a second passivation layer on one of said plurality of surfaces of said unitized body; and f) forming a second layer of metal that extends through said second passivation layer to contact said first rerouting metal layer.
Claim 30
Dependent Claim
19 words
A method as recited in claim 25, wherein said second layer of metal extends over said second passivation layer.
Claim 31
Dependent Claim
27 words
A method as recited in claim 25, wherein said wafer, said first, and said second polymeric insulation layers have coefficients of thermal expansion that are approximately equal.
Claim 32
Dependent Claim
23 words
A method as recited in claim 25, wherein said first polymeric insulation layer has a dielectric constant that is less than approximately 4.
Claim 33
Dependent Claim
28 words
A method as recited in claim 25, further comprising between said steps (b) and (c) the step of forming an adhesive layer on said second polymeric insulation layer.
Claim 34
Dependent Claim
12 words
A method as recited in claim 29, wherein said adhesive is polymeric.
Claim 35
Dependent Claim
19 words
A method as recited in claim 30, wherein said first and second polymeric layers and said adhesive are polyimides.
Claim 36
Dependent Claim
19 words
A method as recited in claim 31, wherein said polyimides include one of BPDA-PDA, Dupont 5878, PMDA-ODA and Thermid.
Claim 37
Dependent Claim
62 words
A method as recited in claim 30, further comprising the step of heating to stabilize said polymeric adhesive without substantial curing and wherein said bonding step (d) is accomplished by bringing a surface of one of said plurality of integrated circuit chips into contact with a surface of another chip, said adhesive polymer layer therebetween, and fully curing said adhesive polymer layer.
Claim 38
Dependent Claim
71 words
A method as recited in claim 25, further comprising between said steps (b) and (c) the step of heating to stabilize said second polymeric insulation layer without curing, and wherein said bonding step (d) is accomplished by bringing a surface of one of said plurality of integrated circuit chips into contact with a surface of another chip, said second polymeric insulation layer therebetween, and fully cuing said second polymeric insulation layer.
Claim 39
Dependent Claim
46 words
The method as recited in claim 25, wherein during said step of forming said plurality of integrated circuit chips on said wafer, said first passivation layer is etched to form an edge surface, such that during said dicing step said first passivation layer is not cut.
Claim 40
Dependent Claim
36 words
The method as recited in of claim 35, wherein said first polymer material is disposed over said edge surface of said first passivation layer, such that during said dicing step said first polymer material is cut.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-25 | 1999-06-26 | 1999-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-25 | 2003-06-26 | 2003-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-25 | 2007-06-26 | 2007-12-26 | $7700.00 | Window Closed / Lapsed |