US5596226A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor chip having a chip metal layer and a transfer metal and corresponding electronic module
Assignee: International Business Machines Corp
•
Filing: 1994-09-06
•
Granted: 1997-01-21
•
Expires: 2014-09-06
Abstract
Abstract A fabrication method including a semiconductor chip kerf clear process and a resulting semiconductor chip and electronic module formed thereby. The fabrication method includes providing a wafer comprising a plurality of integrated circuit chips having kerf regions between them. Chip metallization is present within the kerf regions. A photolithography process is used to protect the wafer exposing only the kerf regions. Next, the wafer is etched, clearing the chip metallization from the kerf regions. The wafer is then diced and the chips are stacked to form a monolithic electronic module. A side surface of the electronic module is processed to expose transfer metals extending thereto, thereby facilitating electrical connection to the chips within the electronic module. Specific details of the fabrication method, resulting integrated circuit chips and monolithic electronic module are set forth.
Inventors
- 👤 Kenneth E. Beilstein, Jr.
- 👤 Claude L. Bertin
- 👤 Timothy H. Daubenspeck
- 👤 Wayne J. Howell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-10 02:37
CPC Classifications
H; H10; H10P; H10P95/00; H10W; H10W90/00; H10W70/00; H10W70/60; H10W72/00; H10W72/834; H10W90/20; H10W90/297
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
115 words
A bare integrated circuit (IC) chip comprising: a support layer; a chip metal layer composed of a first type of metal, said chip metal layer being mechanically coupled to said support layer, and a transfer metal layer integral to said bare IC chip and composed of said first type of metal, said transfer metal layer being mechanically coupled to said support layer wherein said transfer metal layer extends from above circuitry of said bare IC chip to an edge surface of said IC chip for facilitating electrical contact to said circuitry from said edge surface; and wherein at said edge surface the chip metal layer is coplanar with and spaced from the transfer metal layer.
Claim 2
Dependent Claim
115 words
A bare integrated circuit (IC) chip comprising: a support layer; a chip metal layer composed of a first type of metal, said chip metal layer being mechanically coupled to said support layer, and a transfer metal layer integral to said bare IC chip and composed of said first type of metal, said transfer metal layer being mechanically coupled to said support layer wherein said transfer metal layer extends from above circuitry of said bare IC chip to an edge surface of said IC chip for facilitating electrical contact to said circuitry from said edge surface; and wherein at said edge surface the chip metal layer is coplanar with and spaced from the transfer metal layer.
Claim 3
Dependent Claim
126 words
An electronic module comprising: a plurality of stacked bare integrated circuit (IC) chips, wherein each IC chip of said plurality of stacked IC chips has a support layer, a first chip metal layer composed of a first metal and a transfer metal lead composed of said first metal, wherein said first chip metal layer and said transfer metal lead are mechanically coupled to said support layer and wherein said transfer metal lead is integral to said IC chip and extends from above circuitry of said IC chip to an edge surface of said IC chip for facilitating electrical contact to said circuitry from said edge surface, wherein at said edge surface said first chip metal layer is coplanar with and spaced from said transfer metal lead.
Claim 4
Dependent Claim
126 words
An electronic module comprising: a plurality of stacked bare integrated circuit (IC) chips, wherein each IC chip of said plurality of stacked IC chips has a support layer, a first chip metal layer composed of a first metal and a transfer metal lead composed of said first metal, wherein said first chip metal layer and said transfer metal lead are mechanically coupled to said support layer and wherein said transfer metal lead is integral to said IC chip and extends from above circuitry of said IC chip to an edge surface of said IC chip for facilitating electrical contact to said circuitry from said edge surface, wherein at said edge surface said first chip metal layer is coplanar with and spaced from said transfer metal lead.
References Cited (Backward Citations)
DE1212279B
Cited
US3859127A
Cited
JPS57154838A
Cited
EP0075945A2
Cited
EP0206696A2
Cited
US5196378A
Cited
US5391921A
Cited
US5104820A
Cited
US5103287A
Cited
US5126231A
Cited
JPH0448756A
Cited
US5397916A
Cited
US5266833A
Cited
US5259925A
Cited
US5324687A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-21 | 2000-07-22 | 2001-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-21 | 2004-07-22 | 2005-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-21 | 2008-07-22 | 2009-01-21 | $7700.00 | Window Closed / Lapsed |