Integrated circuit bus structure

Claim 1

A bus structure for an electronic system formed of a plurality of discrete integrated circuits performing different and at least certain of data processing, addressing, memory, and input/output signal conditioning functions, the bus structure comprising: a plurality of semiconductor integrated circuit dies each having first and second opposed major surfaces and a peripheral edge formed therebetween, the plurality of integrated circuit dies disposed in a spaced, parallel arrangement; integrated circuitry formed on each integrated circuit die for performing at lest one of data processing, addressing, memory and input/output signal conditioning functions, the integrated circuitry differing on at least certain of the integrated circuit dies; each of the integrated circuit dies including a plurality of terminal pads disposed on the peripheral edge thereof and electrically connected to the integrated circuitry on each integrated circuit die; the terminal pads on each integrated circuit die being arranged in a predetermined, positional electrical signal bus arrangement identical for all of the integrated circuit dies in the electronic system for electrical signal communication to and from each of the plurality of integrated circuit dies; and electrical conductor means, disposed in electrical signal communication with at least certain of the terminal pads on certain of the integrated circuit dies, to form a multi-bit, parallel bus interconnecting each of the plurality of integrated circuit dies in the electronic system.