EP0206696A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Multi-layer semiconductor device
Assignee: Fujitsu Ltd
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Filing: 1986-06-13
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Granted: —
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Expires: 2006-06-13
Abstract
Abstract A multi-layer semiconductor device comprising: a stacked wafer body (7) consisting of a plurality of sets (4) of two semiconductor wafers (1) and a heat sink plate (3) interposed therebetween, an end of the heat sink plate (3) of each set (4) of wafers being exposed at at least one of the side surfaces of the stacked wafer body (7), there being an intermediate connecting circuit (8) provided for connecting circuits in each set of wafers (4), the intermediate connecting circuit (9) being provided on at least one side surface other than the surface at which the ends of the heat skin plates (3) are exposed.
Inventors
- 👤 Takashi Kato
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 21:14
CPC Classifications
H; H10; H10W; H10W40/00; H10W40/10; H10W90/00; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/682; H10W72/00; H10W72/01; H10W72/50; H10W72/541; H10W72/5449; H10W72/551; H10W72/552; H10W72/5524; H10W72/834; H10W90/20; H10W90/288; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
94 words
A multi-layer semiconductor device comprising: a stacked wafer body comprising a plurality of sets of two semiconductor wafers and a heat sink plate interposed therebetween, an end of said heat sink plate of each set of wafers being exposed at at least one of the side surfaces of said stacked wafer body, and an intermediate connectin circuit for connecting circuits in each of the sets of wafers, said intermediate connecting circuit being provided on at least one side surface other than the surface at which the ends of said heat sink plates are exposed.
Claim 2
Dependent Claim
94 words
A multi-layer semiconductor device comprising: a stacked wafer body comprising a plurality of sets of two semiconductor wafers and a heat sink plate interposed therebetween, an end of said heat sink plate of each set of wafers being exposed at at least one of the side surfaces of said stacked wafer body, and an intermediate connectin circuit for connecting circuits in each of the sets of wafers, said intermediate connecting circuit being provided on at least one side surface other than the surface at which the ends of said heat sink plates are exposed.
Claim 3
Dependent Claim
17 words
A multi-layer semiconductor device according to claim 1, wherein said heat sink plate is aluminum or copper.
Claim 4
Dependent Claim
31 words
A multi-layer semiconductor device according to claim 2, wherein the thickness of the aluminum or copper sink plate is 7 0 µ m or more or 42 µm or more respectively.
Claim 5
Dependent Claim
23 words
A multi-layer semiconductor device according to any preceding claim, wherein exposed ends of said heat sink plates are connected to a heat sink.
Claim 6
Dependent Claim
42 words
A multi-layer semiconductor device according to claim /4, wherein the connection of the exposed ends of said heat sink plates to / heat sink is carried out by connecting extended ends of the heat sink plates to the heat sink, having grooves.
Claim 7
Dependent Claim
35 words
A multi-layer semiconductor. devic according any preceding heat sink end or opposite to any preceding claim, wherein the expcsed heat sink end side is the back or opposite side to the intermediate connecting circuit side.
Claim 8
Dependent Claim
17 words
A multi-layer semiconductor device according to/claim, wherein on the intermediate connecting circuit side embedded electrodes are provided.
References Cited (Backward Citations)
No citation records indexed.
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