US4822755A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating large area semiconductor arrays
Assignee: Xerox Corp
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Filing: 1988-04-25
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Granted: 1989-04-18
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Expires: 2008-04-25
Abstract
Abstract A method for separating chips formed on a silicon substrate is provided which uses a combination of reactive ion etching techniques combined with orientation etching to yield integrated chips having edges which can be more precisely butted together to form large area arrays.
Inventors
- 👤 William G. Hawkins
- 👤 Donald J. Drake
- 👤 Michael R. Campanelli
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 11:29
CPC Classifications
B; B41; B41J; B41J2/00; B41J2/005; B41J2/01; B41J2/135; B41J2/16; B41J2/1621; B41J2/1626; B41J2/1628; B41J2/1601; B41J2/1623; B41J2/1629; B41J2/164; B41J2/1642; H; H10; H10D; H10D62/00; H10D62/10; H10D62/117; H10P; H10P50/00; H10P50/60; H10P50/64; H10P50/642; B41J2202/00; B41J2202/01; B41J2202/13; Y; Y10; Y10S; Y10S438/00; Y10S438/928
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
140 words
A method for separating integrated circuit chips formed on a crystalline substrate comprising the steps of (a) forming a plurality of vertical trenches along predetermined intersecting lateral boundaries on the top surface of said substrate by a reactive ion etch process, (b) filling in said trenches with an etchable material, (c) forming a plurality of integrated circuits on the surface of said substrate with said lateral boundaries, (d) passivating both surfaces of said substrate, (e) and etching a plurality of grooves on the back of the wafer in general alignment with said vertical trenches, said etching being adapted to etch into, and free said trenches from said etchable material, whereby said integrated circuits are separated by the combined action of said top and bottom etching steps, said circuits being formed with planar butting surfaces created by the vertical trench formation.
Claim 2
Independent Claim
140 words
A method for separating integrated circuit chips formed on a crystalline substrate comprising the steps of (a) forming a plurality of vertical trenches along predetermined intersecting lateral boundaries on the top surface of said substrate by a reactive ion etch process, (b) filling in said trenches with an etchable material, (c) forming a plurality of integrated circuits on the surface of said substrate with said lateral boundaries, (d) passivating both surfaces of said substrate, (e) and etching a plurality of grooves on the back of the wafer in general alignment with said vertical trenches, said etching being adapted to etch into, and free said trenches from said etchable material, whereby said integrated circuits are separated by the combined action of said top and bottom etching steps, said circuits being formed with planar butting surfaces created by the vertical trench formation.
Claim 3
Dependent Claim
12 words
The method of claim 1 wherein said substrate is a silicon wafer.
Claim 4
Dependent Claim
28 words
The method of claim 2 including the further steps of forming a p+ layer adjoining said trenches, said p+ layer serving as a stop to the groove etch.
Claim 5
Dependent Claim
25 words
The method of claim 2 including formation of a buried n-layer and using a reverse biased junction as a stop for the ODE groove etch.
Claim 6
Dependent Claim
36 words
The method of claim 3 wherein said p+ layer is formed by diffusion into the top surface of the substrate on both sides of the trenches, extending a vertical distance substantially equal to the trench sides.
Claim 7
Dependent Claim
40 words
The method of claim 3 wherein said p+ layer is formed below the surface of said wafer and near the bottom of said trench and including the further step of forming a lightly doped p- layer above said p+ layer.
Claim 8
Dependent Claim
22 words
The method of claim 3 wherein said trench is formed with a width of 3 microns and depth of approximately 10 microns.
Claim 9
Dependent Claim
22 words
The method of claim 2 including the further step of the step of oxidizing the trench and filling said trench with polysilicon.
Claim 10
Dependent Claim
30 words
The method of claim 8 wherein said orientation etch is interrupted by a wet oxide etching step to etch through the oxide layer formed at the bottom of the trench.
Claim 11
Dependent Claim
11 words
The method of claim 2 wherein said substrate is p+ silicon.
Claim 12
Dependent Claim
18 words
The method of claim 2 wherein said substrate is p- silicon having a resistivity of approximately 0.01 ohm/cm.
Claim 13
Dependent Claim
45 words
The method of claim 1 wherein said bottom grooves are formed by a dicing procedure that forms a groove whose centerline is offset from the centerline of said trenches and including an additional step of repeating the chips by fracturing along the trench groove interface.
Claim 14
Dependent Claim
46 words
The method of claim 2 wherein said integrated circuits form a resistor plate for an ink jet printhead and including the further step of bonding a second silicon wafer to the top of said resistive plate to form a channel plate for a ink jet printhead.
References Cited (Backward Citations)
US3689389A
Cited
JPS5245879A
Cited
JPS5325350A
Cited
JPS5591138A
Cited
US4295924A
Cited
US4358340A
Cited
US4409319A
Cited
US4523369A
Cited
US4589952A
Cited
JPS60157236A
Cited
US4542397A
Cited
US4526631A
Cited
JPS61216338A
Cited
US4604161A
Cited
US4612554A
Cited
US4661201A
Cited
US4670092A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-17 | 1992-10-17 | 1993-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-17 | 1996-10-17 | 1997-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-17 | 2000-10-17 | 2001-04-18 | $7700.00 | Window Closed / Lapsed |