US5561622A — Integrated memory cube structure

Claim 1

Independent Claim 215 words

An integrated memory cube which to external circuitry emulates a single memory chip architecture, said integrated memory cube comprising: a combination memory chip and logic chip stack including (i) N memory chips (wherein N≧2) each having M storage devices (wherein M≧2), along with two substantially parallel planar main surfaces and an edge surface, (ii) a logic chip electrically connected to each of the N memory chips for coordinating external circuitry communication with the N×M storage devices of the stack, said electrically connected logic chip and N memory chips having an integrated memory architecture that emulates to said external circuitry a single memory chip architecture with said N×M storage devices, wherein said external circuitry addresses said stack through said logic chip as said single memory chip architecture, said logic chip also having two parallel planar main surfaces and an edge surface, and (iii) at least one planar main surface of each chip in the stack being coupled to a planar main surface of an adjacent chip in the stack, the edge surfaces of the N memory chips and the edge surface of the logic chip aligning to form at least one side surface of the stack, said stack also having an end surface disposed parallel to the planar main surfaces of the chips in the stack.

Claim 2

Dependent Claim 215 words

An integrated memory cube which to external circuitry emulates a single memory chip architecture, said integrated memory cube comprising: a combination memory chip and logic chip stack including (i) N memory chips (wherein N≧2) each having M storage devices (wherein M≧2), along with two substantially parallel planar main surfaces and an edge surface, (ii) a logic chip electrically connected to each of the N memory chips for coordinating external circuitry communication with the N×M storage devices of the stack, said electrically connected logic chip and N memory chips having an integrated memory architecture that emulates to said external circuitry a single memory chip architecture with said N×M storage devices, wherein said external circuitry addresses said stack through said logic chip as said single memory chip architecture, said logic chip also having two parallel planar main surfaces and an edge surface, and (iii) at least one planar main surface of each chip in the stack being coupled to a planar main surface of an adjacent chip in the stack, the edge surfaces of the N memory chips and the edge surface of the logic chip aligning to form at least one side surface of the stack, said stack also having an end surface disposed parallel to the planar main surfaces of the chips in the stack.

Claim 3

Dependent Claim 214 words

An integrated memory cube architecture comprising: a combination memory chip and logic chip stack including (i) N memory chips (wherein N≧2) each having M storage devices (wherein M≧2), along with two substantially parallel planar main surfaces and an edge surface, (ii) a logic chip electrically connected to each of the N memory chips for coordinating external communication with the N memory chips of the stack, said logic chip also having two parallel planar main surfaces and an edge surface, (iii) at least one planar main surface of each chip in the stack being coupled to a planar main surface of an adjacent chip in the stack, the edge surfaces of the N memory chips and the edge surface of the logic chip aligning to form at least one side surface of the stack, said stack also having an end surface disposed parallel to the planar main surfaces of the chips in the stack, and (iv) wherein one of said two parallel planar main surfaces of said logic chip comprises an upper surface of the logic chip, and wherein said upper surface of the logic chip includes an array of contact pads, at least some of said contact pads of said array of contact pads comprising I/O contacts for external circuitry connection to the stack.

Claim 4

Dependent Claim 214 words

An integrated memory cube architecture comprising: a combination memory chip and logic chip stack including (i) N memory chips (wherein N≧2) each having M storage devices (wherein M≧2), along with two substantially parallel planar main surfaces and an edge surface, (ii) a logic chip electrically connected to each of the N memory chips for coordinating external communication with the N memory chips of the stack, said logic chip also having two parallel planar main surfaces and an edge surface, (iii) at least one planar main surface of each chip in the stack being coupled to a planar main surface of an adjacent chip in the stack, the edge surfaces of the N memory chips and the edge surface of the logic chip aligning to form at least one side surface of the stack, said stack also having an end surface disposed parallel to the planar main surfaces of the chips in the stack, and (iv) wherein one of said two parallel planar main surfaces of said logic chip comprises an upper surface of the logic chip, and wherein said upper surface of the logic chip includes an array of contact pads, at least some of said contact pads of said array of contact pads comprising I/O contacts for external circuitry connection to the stack.

Claim 5

Dependent Claim 35 words

The integrated memory cube of claim 2, wherein the logic chip is disposed at an end of the stack such that the upper surface of the logic chip comprises the end surface of the stack.

Claim 6

Dependent Claim 51 words

The integrated memory cube of claim 3, further comprising a lead frame secured to the stack adjacent its end surface, said lead frame having an inner opening extending therethrough such that at least a portion of the array of contact pads on the upper surface of the logic chip remains exposed.

Claim 7

Dependent Claim 39 words

The integrated memory cube of claim 4, further comprising conventional wirebonding electrically connecting the lead frame and at least some of the exposed contact pads of the array of contact pads on the upper surface of the logic chip.

Claim 8

Dependent Claim 80 words

The integrated memory cube of claim 3, further comprising a spacer layer disposed on the end surface of the stack, said spacer layer having an inner opening extending therethrough and sized to expose at least a portion of the contact pads on the upper surface of the logic chip, said spacer layer having a thickness sufficient to allow formation of T-connects along the at least one side surface of the stack adjacent to the upper surface of the logic chip.

Claim 9

Dependent Claim 49 words

The integrated memory cube of claim 6, further comprising a lead frame secured to on exposed surface of the spacer layer, said lead frame also having an inner opening extending therethrough sized such that the contact pads exposed through the spacer layer are also exposed through the lead frame.

Claim 10

Dependent Claim 33 words

The integrated memory cube of claim 7, further comprising conventional wirebonding electrically connecting the lead frame and at least some of the exposed contact pads on the upper surface of the logic chip.

Claim 11

Dependent Claim 28 words

The integrated memory cube of claim 2, wherein at least two of said contact pads of said array of contact pads are electrically interconnected for logic function programming.

Claim 12

Dependent Claim 39 words

The integrated memory cube of claim 1, wherein the logic chip includes logic means for holding each of said N memory chips of the stack in a sleep mode in response to a control command received from external circuitry.

Claim 13

Dependent Claim 56 words

The integrated memory cube of claim 1, wherein the logic chip is electrically connected to receive an address signal from external circuitry and wherein the logic chip includes logic means for decoding the address signal to identify at least one memory chip of the M memory chips having a memory device addressed by the address signal.

Claim 14

Dependent Claim 26 words

The integrated memory cube of claim 1, wherein the logic chip includes logic means for sequentially refreshing each of the N memory chips in the stack.

Claim 15

Dependent Claim 36 words

The integrated memory cube of claim 12, wherein the logic means for sequentially refreshing includes a counter connected to sequentially track which memory chip of said N memory chips in the stack is to be refreshed.

Claim 16

Dependent Claim 29 words

The integrated memory cube of claim 1, wherein the logic chip includes logic means for regulating a received voltage to an on-chip voltage for powering at a desired level.

Claim 17

Dependent Claim 11 words

The integrated memory cube of claim 1, wherein N equals four.

Claim 18

Dependent Claim 17 words

The integrated memory cube of claim 1, wherein the N memory chips each comprise a RAM chip.

Claim 19

Dependent Claim 58 words

The integrated memory cube of claim 1, wherein at least some of the N memory chips include transfer metallurgy extending to the at least one side surface of the stack, and wherein the integrated memory cube further comprises a metallization pattern disposed on the stack's at least one side surface and electrically connecting the transfer metallurgy extending thereto.

Claim 20

Dependent Claim 39 words

The integrated memory cube of claim 17, wherein the metallization pattern disposed on the stack's at least one side surface electrically connects with the transfer metallurgy extending to the at least one side surface of the stack via T-connects.

Claim 21

Dependent Claim 112 words

The integrated memory cube of claim 18, wherein the logic chip is disposed adjacent to the end surface of said stack and includes transfer metallurgy extending to the at least one side surface of the stack, and wherein the integrated memory cube further comprises a spacer layer covering the logic chip and having an edge aligned with the at least one side surface of the stack, the spacer layer having a width and thickness sufficient to allow T-connects between the transfer metallurgy on the logic chip extending to the at least one side surface of the stack and the metallization pattern disposed on the at least one side surface of the stack.

Claim 22

Dependent Claim 138 words

An integrated memory cube which emulates for external circuitry a single memory chip architecture, said integrated memory cube comprising: N memory chips (wherein N≧2) each having M storage devices (wherein M≧2), each memory chip of said N memory chips comprising a first single chip memory architecture, said N memory chips being laminated together in a stack; and a logic circuit electrically connected to each of the N memory chips for coordinating external circuitry communication with the N×M storage devices of the stack, said electrically connected logic circuit and N memory chips having an integrated memory architecture which emulates for said external circuitry a second single chip memory architecture having N×M storage devices, said second single chip memory architecture comprising a different memory chip architecture from said first single chip memory architecture of each of said N memory chips.

Claim 23

Dependent Claim 138 words

An integrated memory cube which emulates for external circuitry a single memory chip architecture, said integrated memory cube comprising: N memory chips (wherein N≧2) each having M storage devices (wherein M≧2), each memory chip of said N memory chips comprising a first single chip memory architecture, said N memory chips being laminated together in a stack; and a logic circuit electrically connected to each of the N memory chips for coordinating external circuitry communication with the N×M storage devices of the stack, said electrically connected logic circuit and N memory chips having an integrated memory architecture which emulates for said external circuitry a second single chip memory architecture having N×M storage devices, said second single chip memory architecture comprising a different memory chip architecture from said first single chip memory architecture of each of said N memory chips.

Claim 24

Dependent Claim 19 words

The integrated memory cube of claim 20, wherein said logic circuit comprises a logic chip laminated to said stack.

Claim 25

Dependent Claim 15 words

The integrated memory cube of claim 20, wherein said logic circuit comprises a memory controller.

Claim 26

Dependent Claim 145 words

An integrated multichip memory module which emulates to external circuitry a single chip memory architecture, said integrated multichip memory module comprising: a memory subunit having N memory chips (wherein N≧2), each memory chip of the memory subunit having M memory devices (wherein M≧2), along with two substantially parallel planar main surfaces and an edge surface, at least one planar main surface of each memory chip being coupled to a planar main surface of an adjacent memory chip of the memory subunit such that said memory subunit has a stack structure; and logic means electrically connected to each of the N memory chips for coordinating external circuitry communication with said N memory chips of said memory subunit such that an integrated memory architecture with said N×M memory devices; exists which appears to said external circuitry to comprise said single chip memory structure with N×M memory devices.

Claim 27

Dependent Claim 145 words

An integrated multichip memory module which emulates to external circuitry a single chip memory architecture, said integrated multichip memory module comprising: a memory subunit having N memory chips (wherein N≧2), each memory chip of the memory subunit having M memory devices (wherein M≧2), along with two substantially parallel planar main surfaces and an edge surface, at least one planar main surface of each memory chip being coupled to a planar main surface of an adjacent memory chip of the memory subunit such that said memory subunit has a stack structure; and logic means electrically connected to each of the N memory chips for coordinating external circuitry communication with said N memory chips of said memory subunit such that an integrated memory architecture with said N×M memory devices; exists which appears to said external circuitry to comprise said single chip memory structure with N×M memory devices.

Claim 28

Dependent Claim 22 words

The integrated multichip memory module of claim 23, wherein said logic means; comprises a logic chip mechanically coupled to said memory subunit.

Claim 29

Dependent Claim 38 words

The integrated multichip memory module of claim 23, wherein said logic means includes means for holding said N memory chips of said memory subunit in a sleep mode in response to a control command received from external circuitry.

Claim 30

Dependent Claim 65 words

The integrated multichip memory module of claim 23, wherein said logic means is connected to receive an address signal for said single chip memory structure from said external circuitry and wherein said logic means includes means for decoding said address signal to identify at least one of said N memory chips of said memory subunit having an addressed memory device identified by the address signal.

Claim 31

Dependent Claim 27 words

The integrated multichip memory module of claim 23, wherein said logic means includes means for sequentially refreshing each of said N memory chips of said memory subunit.

Claim 32

Dependent Claim 35 words

The integrated multichip memory module of claim 27, wherein said means for sequentially refreshing includes a counter connected for sequentially tracking a last refreshed memory chip of said N memory chips in said memory subunit.

Claim 33

Dependent Claim 30 words

The integrated multichip memory module of claim 23, wherein said memory subunit is powered at a first voltage level and said logic means is powered at a second voltage level.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1999-10-01	2000-04-01	2000-10-01	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2003-10-01	2004-04-01	2004-10-01	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2007-10-01	2008-04-01	2008-10-01	$7700.00	Window Closed / Lapsed

Integrated memory cube structure

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