US5780323A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fabrication method for metal-to-metal antifuses incorporating a tungsten via plug
Assignee: Microsemi SoC Corp
•
Filing: 1996-11-12
•
Granted: 1998-07-14
•
Expires: 2016-11-12
Abstract
Abstract According to a first aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer under a plug of an electrically conductive material disposed between two metallization layers. According to a second aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer comprising a first nitride/first amorphous silicon/second nitride/second amorphous silicon sandwich under a plug of an electrically conductive material lined with titanium disposed between two metallization layers. In this aspect of the invention the titanium is allowed to react with the second amorphous silicon layer to form an electrically conductive silicide. This leaves the first nitride/first amorphous silicon/second nitride as the antifuse material layer while guaranteeing a strict control on the thickness of the antifuse material layer for assuring strict control over its respective breakdown or programming voltage. According to a third aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer disposed over a plug of an electrically conductive material disposed between two metallization layers.
Inventors
- 👤 Abdul R. Forouhi
- 👤 Frank W. Hawley
- 👤 John L. McCollum
- 👤 Yeouchung Yen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:40
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491; H10W20/01; H10W20/031; H10W20/064; H10W20/065
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
112 words
A method of fabricating an antifuse disposed on an integrated circuit comprising the steps of: a. disposing a first metallization layer on an insulating portion of the integrated circuit; b. disposing an antifuse material layer over said first metallization layer; c. disposing an etch-stop layer over said antifuse material layer; d. patterning and etching said antifuse material layer; e. disposing a dielectric layer over said etch-stop layer; f. etching a via entirely through said dielectric layer to expose said etch-stop layer; g. disposing a plug of a conductive material within said via; h. disposing a second metallization layer over said dielectric layer and said plug and in electrical contact with said plug.
Claim 2
Independent Claim
112 words
A method of fabricating an antifuse disposed on an integrated circuit comprising the steps of: a. disposing a first metallization layer on an insulating portion of the integrated circuit; b. disposing an antifuse material layer over said first metallization layer; c. disposing an etch-stop layer over said antifuse material layer; d. patterning and etching said antifuse material layer; e. disposing a dielectric layer over said etch-stop layer; f. etching a via entirely through said dielectric layer to expose said etch-stop layer; g. disposing a plug of a conductive material within said via; h. disposing a second metallization layer over said dielectric layer and said plug and in electrical contact with said plug.
Claim 3
Dependent Claim
16 words
The method of claim 1 wherein step (g) is accomplished by means of chemical vapor deposition.
Claim 4
Dependent Claim
17 words
The method of claim 2 wherein tungsten is the material deposited by means of chemical vapor deposition.
Claim 5
Dependent Claim
19 words
The method of claim 1 wherein step (g) is accomplished by means of sputter deposition of a conductive metal.
Claim 6
Independent Claim
170 words
A method of fabricating an antifuse disposed on an integrated circuit comprising the steps of: a. disposing a first metallization layer on an insulating portion of the integrated circuit; b. disposing an antifuse material layer over said first metallization layer, said antifuse material layer including a first layer of amorphous silicon disposed on said first metallization layer and a second layer of an insulating material disposed on said first layer, said insulating material being a material other than amorphous silicon; c. disposing an electrically conductive etch-stop layer over said antifuse material layer; d. patterning and etching said antifuse material layer; e. disposing a dielectric layer over said first amorphous silicon layer; f. etching a via entirely through said dielectric layer to expose said etch-stop layer; g. disposing an electrically conductive material in the form of a plug in said via to form an electrical path from said electrically conductive etch-stop layer through said dielectric layer; and h. disposing a second metallization layer over and in electrical contact with said plug.
Claim 7
Independent Claim
170 words
A method of fabricating an antifuse disposed on an integrated circuit comprising the steps of: a. disposing a first metallization layer on an insulating portion of the integrated circuit; b. disposing an antifuse material layer over said first metallization layer, said antifuse material layer including a first layer of amorphous silicon disposed on said first metallization layer and a second layer of an insulating material disposed on said first layer, said insulating material being a material other than amorphous silicon; c. disposing an electrically conductive etch-stop layer over said antifuse material layer; d. patterning and etching said antifuse material layer; e. disposing a dielectric layer over said first amorphous silicon layer; f. etching a via entirely through said dielectric layer to expose said etch-stop layer; g. disposing an electrically conductive material in the form of a plug in said via to form an electrical path from said electrically conductive etch-stop layer through said dielectric layer; and h. disposing a second metallization layer over and in electrical contact with said plug.
Claim 8
Independent Claim
180 words
A method of fabricating an antifuse disposed on an integrated circuit comprising the steps of: a. disposing a first metallization layer on an insulating portion of the integrated circuit; b. disposing an antifuse material layer over said first metallization layer; c. disposing a first layer of amorphous silicon over said antifuse material layer; d. patterning and etching said antifuse material layer; e. disposing a dielectric layer over said first amorphous silicon layer; f. etching a via entirely through said dielectric layer and partially into said first amorphous silicon layer; g. disposing a layer of titanium over said via; h. thermally reacting said layer of titanium and said first layer of amorphous silicon to form a region of electrically conductive titanium silicide in the vicinity of said via and extending vertically substantially entirely through said first amorphous silicon layer; i. depositing a layer of an electrically conductive material in the form of a plug in said via substantially filling said via; and j. disposing a second metallization layer over said dielectric layer and over and in electrical contact with said plug.
Claim 9
Independent Claim
180 words
A method of fabricating an antifuse disposed on an integrated circuit comprising the steps of: a. disposing a first metallization layer on an insulating portion of the integrated circuit; b. disposing an antifuse material layer over said first metallization layer; c. disposing a first layer of amorphous silicon over said antifuse material layer; d. patterning and etching said antifuse material layer; e. disposing a dielectric layer over said first amorphous silicon layer; f. etching a via entirely through said dielectric layer and partially into said first amorphous silicon layer; g. disposing a layer of titanium over said via; h. thermally reacting said layer of titanium and said first layer of amorphous silicon to form a region of electrically conductive titanium silicide in the vicinity of said via and extending vertically substantially entirely through said first amorphous silicon layer; i. depositing a layer of an electrically conductive material in the form of a plug in said via substantially filling said via; and j. disposing a second metallization layer over said dielectric layer and over and in electrical contact with said plug.
Claim 10
Dependent Claim
23 words
The method of claim 6 further comprising the step of depositing a barrier layer over said layer of titanium and under said plug.
Claim 11
Dependent Claim
36 words
The method of claim 7 wherein said barrier layer is a material selected from the group consisting of: TiN, TiW, TiWN, W, TiC, WC and combinations of two or more of any of the foregoing materials.
Claim 12
Dependent Claim
51 words
The method of claim 6 wherein step (b) comprises the sub-steps of: i. disposing a first silicon nitride layer over said first metallization layer; ii. disposing a second amorphous silicon layer over said first silicon nitride layer; and iii. disposing a second silicon nitride layer over said second amorphous silicon layer.
Claim 13
Dependent Claim
101 words
The method of claim 9 wherein step (a) comprises the sub-steps of: i. disposing a first barrier layer of a material selected from the group consisting of: TiN, TiW, TiWN, W, TiC, WC and combinations of two or more of any of the foregoing materials; ii. disposing a first layer of aluminum over said first barrier layer; and iii. disposing a second barrier layer over said first layer of aluminum, said second barrier layer of a material selected from the group consisting of: TiN, TiW, TiWN, W, TiC, WC and combinations of two or more of any of the foregoing materials.
Claim 14
Dependent Claim
26 words
The method of claim 6 wherein step (i) is accomplished by Chemical Vapor Deposition of a material selected from the group consisting of W and TiN.
Claim 15
Independent Claim
231 words
A method of fabricating an antifuse disposed on an integrated circuit comprising the steps of: a. disposing a first metallization layer on an insulating portion of the integrated circuit; b. disposing an antifuse material layer over said first metallization layer, said antifuse material layer including a first layer of amorphous silicon disposed on said first metallization layer and a second layer of an insulating material disposed on said first layer of amorphous silicon, said second layer of an insulating material being a material other than amorphous silicon; c. disposing a second layer of amorphous silicon over said antifuse material layer; d. patterning and etching said antifuse material layer and said layer of amorphous silicon; e. disposing a dielectric layer over said second amorphous silicon layer; f. etching a via entirely through said dielectric layer and partially into said second amorphous silicon layer; g. disposing a layer of Ti over said via and in contact with said second amorphous silicon layer; h. thermally reacting said Ti and said second layer of amorphous silicon to form a region of electrically conductive titanium silicide in the vicinity of said via and extending vertically substantially entirely through said second layer of amorphous silicon; i. disposing a plug of an electrically conductive material in said via and substantially filling said via; and j. disposing a second metallization layer over and in electrical contact with said plug.
Claim 16
Independent Claim
231 words
A method of fabricating an antifuse disposed on an integrated circuit comprising the steps of: a. disposing a first metallization layer on an insulating portion of the integrated circuit; b. disposing an antifuse material layer over said first metallization layer, said antifuse material layer including a first layer of amorphous silicon disposed on said first metallization layer and a second layer of an insulating material disposed on said first layer of amorphous silicon, said second layer of an insulating material being a material other than amorphous silicon; c. disposing a second layer of amorphous silicon over said antifuse material layer; d. patterning and etching said antifuse material layer and said layer of amorphous silicon; e. disposing a dielectric layer over said second amorphous silicon layer; f. etching a via entirely through said dielectric layer and partially into said second amorphous silicon layer; g. disposing a layer of Ti over said via and in contact with said second amorphous silicon layer; h. thermally reacting said Ti and said second layer of amorphous silicon to form a region of electrically conductive titanium silicide in the vicinity of said via and extending vertically substantially entirely through said second layer of amorphous silicon; i. disposing a plug of an electrically conductive material in said via and substantially filling said via; and j. disposing a second metallization layer over and in electrical contact with said plug.
Claim 17
Dependent Claim
16 words
The method of claim 12 wherein said second layer of an insulating material includes silicon nitride.
Claim 18
Dependent Claim
49 words
The method of claim 12 wherein step (a) comprises the sub-steps of: i. disposing a first barrier layer over an insulating portion of the integrated circuit; ii. disposing a conductive metal layer over said first barrier layer; and iii. disposing a second barrier layer over said conductive metal layer.
Claim 19
Dependent Claim
33 words
The method of claim 12 wherein step (i) comprises the sub-steps of: i. disposing a barrier layer over said titanium layer; and ii. CVD deposition of said electrically conductive material within said via.
Claim 20
Dependent Claim
12 words
The method of claim 12 wherein said electrically conductive material is tungsten.
References Cited (Backward Citations)
US3634929A
Cited
US3675090A
Cited
US3717852A
Cited
US3877049A
Cited
US4271582A
Cited
US4322822A
Cited
US4238839A
Cited
US4455495A
Cited
US4261763A
Cited
US4399372A
Cited
US4357622A
Cited
US4565712A
Cited
US4323986A
Cited
US4424578A
Cited
US4499557A
Cited
US4420820A
Cited
US4361599A
Cited
US4441247A
Cited
US4585490A
Cited
EP0081226A3
Cited
US4507756A
Cited
US4507757A
Cited
EP0092871B1
Cited
US4489481A
Cited
US4590589A
Cited
US4617723A
Cited
US4569121A
Cited
US4569120A
Cited
US4847732A
Cited
US4628590A
Cited
US4535528A
Cited
US4796075A
Cited
EP0162529B1
Cited
US4651409A
Cited
US4602420A
Cited
US4751197A
Cited
US4912066A
Cited
US4678889A
Cited
US4924287A
Cited
US5087591A
Cited
US4748490A
Cited
US4949084A
Cited
EP0224418B1
Cited
US4647340A
Cited
US4943538A
Cited
US5134457A
Cited
US5266829A
Cited
US4823181A
Cited
US4899205A
Cited
US5166901A
Cited
US4876220A
Cited
US4881114A
Cited
US4893167A
Cited
US4916809A
Cited
US4740485A
Cited
US4721868A
Cited
US4732865A
Cited
US4792835A
Cited
US4786904A
Cited
US4795722A
Cited
US4981813A
Cited
US4839864A
Cited
US4796074A
Cited
US4800176A
Cited
US4897836A
Cited
EP0315421B1
Cited
EP0323078A3
Cited
US4822753A
Cited
US4882611A
Cited
DE3927033A1
Cited
US5210598A
Cited
US4937475B1
Cited
US4937475A
Cited
US5093711A
Cited
US4920072A
Cited
US4910418A
Cited
US5113238A
Cited
US4933898A
Cited
US5010039A
Cited
US5008855A
Cited
EP0671767A3
Cited
US4914055A
Cited
EP0414361A3
Cited
EP0416903A3
Cited
US5021849A
Cited
US5006673A
Cited
EP0436387A3
Cited
US5272369A
Cited
US5272101A
Cited
EP0452091B1
Cited
US5070384A
Cited
US5181096A
Cited
EP0455414A1
Cited
US5126282A
Cited
US5061646A
Cited
US5059555A
Cited
US5106773A
Cited
US5095362A
Cited
US5087958A
Cited
US5099149A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-13 | 2002-01-12 | 2002-07-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-13 | 2006-01-12 | 2006-07-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-13 | 2010-01-12 | 2010-07-14 | $7700.00 | Window Closed / Lapsed |