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EP0323078A3 Expired / Lapsed EP ⏱️ 0.0 years remaining

Electrically-programmable low-impedance anti-fuse element

Assignee: Microsemi SoC Corp
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Filing: 1988-12-14
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Granted: —
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Expires: 2008-12-14
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Abstract

Abstract Electrically-programmable low-impedance anti-fuses are disclosed having capacitor-like structure with very low leakage before programming and a low resistance after programming. The electrically-programmable low-impedance anti-­ fuses (13, 15) of the present invention include a first conductive electrode (12a, 12b) which may be formed as a diffusion region in a semiconductor substrate (10) or may be formed from a semiconductor material, such as polysilicon, located above and insulated from the substrate. A dielectric layer (14), which, in a preferred embodiment includes a first layer of silicon dioxide (16), a second layer of silicon nitride (18) and a third layer of silicon dioxide (20), is disposed over the first electrode. A second electrode (22a, 22b) is formed over the dielectric layer from a semiconductor material such as polysilicon, or a metal having a barrier metal underneath. At least one of the two electrodes of each anti-fuse is highly-doped or implanted with arsenic such that high concentrations of arsenic exist at the interface between the electrode and the dielectric layer. This arsenic will combine with other material and flow into the anti-fuse filament after programmed to form a low resistance controllable anti-fuse link. Circuitry is provided which allows the anti-fuse of the present invention to be programmed by application of a suitable programming voltage to input-output pins of the integrated circuit containing the anti-­ fuse. Where more than one anti-fuse is to be programmed using the programming voltage applied at the input-output terminals, other additional input-output terminals may serve as address inputs to specify the anti-fuse to be programmed. In another embodiment of the present invention a programmable read-only memory array comprised of memory cells including a anti-fuse in combination with a single transistor. X-address and Y-address decoder circuits are provided to both program and read the contents of any selected memory cell in the array.

Inventors

  • 👤 Esmat Zaghloul Hamdy
  • 👤 John Lynn Mccollum
  • 👤 Amr Mohamed Mohsen

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-29 17:12
CPC Classifications
H; H10; H10B; H10B20/00; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

EP0041770A2 Cited
EP0068058A1 Cited
EP0078165A2 Cited
EP0244530A2 Cited
EP0250078A2 Cited

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