EP0244530A2
Expired / Lapsed
EP
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Thin oxide fuse in an integrated circuit
Assignee: American Microsystems Holding Corp
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Filing: 1986-09-30
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Granted: —
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Expires: 2006-09-30
Abstract
Abstract An oxide fuse formed by a thin layer of oxide dielectric between a lower electrode substrate and an upper electrode. A fuse-programming bias of approximately 15 V causes Fowler-Nordheim tunneling at low temperature to damage the dielectric layer, and shorts the upper and lower electrodes together. The oxide layer is advantageously formed simultaneously with the gate oxide layer in an EEPROM.
Inventors
- 👤 Sun Chiao
- 👤 Chen-Chin Wang
- 👤 Tarsaim Lal Batra
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 11:56
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
119 words
A fuse in an integrated circuit formed in and on an upper surface of a semiconductor substrate, comprising: a lower electrode region in the substrate adjacent the surface; an oxide layer formed in and on the surface over the lower electrode region and, under the application of a programming bias, of suitable thickness to conduct a Fowler-Nordheim tunneling current which damages the oxide layer; and an upper electrode disposed over the oxide layer, connectable in a circuit with the substrate to apply a programming bias through the oxide layer between the upper and lower electrodes, and formed of material which, when the oxide is damaged by Fowler-Nordheim tunneling current, forms an electrically conductive connection to the lower electrode region.
Claim 2
Dependent Claim
119 words
A fuse in an integrated circuit formed in and on an upper surface of a semiconductor substrate, comprising: a lower electrode region in the substrate adjacent the surface; an oxide layer formed in and on the surface over the lower electrode region and, under the application of a programming bias, of suitable thickness to conduct a Fowler-Nordheim tunneling current which damages the oxide layer; and an upper electrode disposed over the oxide layer, connectable in a circuit with the substrate to apply a programming bias through the oxide layer between the upper and lower electrodes, and formed of material which, when the oxide is damaged by Fowler-Nordheim tunneling current, forms an electrically conductive connection to the lower electrode region.
Claim 3
Dependent Claim
35 words
A fuse as in Claim 1 wherein the oxide layer thickness is in the range of approximately 80 to 110 angstroms, and wherein the programming bias is in the range of 10 to 15 volts.
Claim 4
Dependent Claim
13 words
A fuse as in Claim 1 wherein the upper electrode comprises polycrystalline silicon.
Claim 5
Dependent Claim
25 words
A fuse as in Claim 1 wherein the lower electrode region is doped with impurities to a higher conductivity than adjacent regions of the substrate.
Claim 6
Dependent Claim
97 words
An EEPROM structure formed on a semiconductor substrate and having memory cells of the type including a thin layer of tunnel oxide on the substrate, a floating gate over the oxide, and a control gate over the floating gate, characterized in that the EEPROM structure further includes a programmable fuse comprising: a lower electrode formed in the substrate; a dielectric layer formed on the substrate simultaneously with, and of the same material as, the tunnel oxide; and an upper electrode formed over the dielectric layer simultaneously with, and of the same material as, one of the gates.
Claim 7
Dependent Claim
97 words
An EEPROM structure formed on a semiconductor substrate and having memory cells of the type including a thin layer of tunnel oxide on the substrate, a floating gate over the oxide, and a control gate over the floating gate, characterized in that the EEPROM structure further includes a programmable fuse comprising: a lower electrode formed in the substrate; a dielectric layer formed on the substrate simultaneously with, and of the same material as, the tunnel oxide; and an upper electrode formed over the dielectric layer simultaneously with, and of the same material as, one of the gates.
References Cited (Backward Citations)
No citation records indexed.
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