Programmable read-only memory

Claim 2

A semiconductor memory cell, comprising: (a) a semiconductive body; (b) a layer of insulating material on a surface of said body; (c) a layer of polysilicon on said insulating layer and including a first region of first type conductivity, a second region of first type conductivity spaced laterally from said first region, a third region of second type conductivity between said first and second regions and forming a first semiconductive junction with said first region, said third region differing in impurity concentration from said first region, and a fourth region of second type conductivity between said first and second regions and forming a second semiconductive junction with said second region, said fourth region at least adjoining said third region and differing in impurity concentration from said second region, said first semiconductive junction having a lower reverse bias breakdown voltage than said second semiconductive junction; (d) a first metal contact forming one terminal of said memory cell and contacting said first region on one side of said first semiconductive junction; (e) a second metal contact forming another terminal of said memory cell and contacting said polysilicon layer on the other side of both said first and second semiconductive junctions and conductively coupled to said second region; (f) the surfaces of said third and fourth regions being free of any metal contact; (g) said first semiconductive junction serving as a programming diode when a voltage is applied across said first and second metal contacts with polarity and magnitude to cause reverse-bias breakdown of said first semiconductive junction.

Claim 3

The invention according to claim 1, wherein said third and fourth regions are merged within a single common region.

Claim 4

The invention according to claim 1, wherein said third and fourth regions comprise regions of different impurity concentration.

Claim 5

The invention according to claim 1, wherein said second region comprises the main body of said polysilicon layer, said third and fourth regions constituting a single region formed within said second region, and said first region being formed within said single region.

Claim 6

The invention according to claim 1, wherein said fourth region comprises the main body of said polysilicon layer, said first and third regions being formed within said fourth region adjoining each other, said second region being formed within said fourth region spaced laterally from said first and third regions.

Claim 7

The invention according to claim 5, wherein said first and third regions form said first semiconductive junction extending the entire depth of said polysilicon layer.

Claim 8

The invention according to claim 5, wherein said first and third regions form said first semiconductive junction mainly at the surface of said polysilicon layer only.

Claim 9

The invention according to claim 2, and further including a metal contact region of high doping concentration of first type conductivity adjacent said second region and to which said second metal contact is applied.

Claim 10

The invention according to claim 8, wherein said second metal contact includes a layer of platinel silicide adherent to said metal contact region and a layer of aluminum deposited on said platinel silicide layer.

Claim 11

The invention according to claim 3, wherein said second metal contact is applied to said second region directly.

Claim 12

The invention according to claim 10, wherein said second metal contact includes a layer of platinel silicide adherent to said second region and a layer of aluminum deposited on said platinel silicide layer.

Claim 13

The invention according to claim 1, wherein said insulating layer is sufficiently thicker than said polysilicon layer as to thermally insulate said polysilicon layer from said semiconductive body.

Claim 14

A semiconductive memory cell, comprising: (a) a semiconductive body; (b) a layer of insulating material on a surface of said body; (c) a layer of polysilicon on said insulating layer and including a first region of first type conductivity, a second region of first type conductivity spaced laterally from said first region, a third region of second type conductivity between said first and second regions and forming a first semiconductive junction with said first region, said third region differing in impurity concentration from said first region, and a fourth region of second type conductivity between said first and second regions and forming a second semiconductive junction with said second region, said fourth region at least adjoining said third region and differing in impurity concentration from said second region, said first semiconductive junction having a lower reverse-bias breakdown voltage than said second semiconductive junction; (d) a relatively thin layer of insulating material on said polysilicon layer provided with openings therein through which electrical contacts can be made to said polysilicon layer; (e) a first metal contact forming one terminal of said memory cell extending over the surface of said polysilicon layer at least a distance overlying said first semiconductive junction and extending through one of said openings so as to contact said first region on one side of said first semiconductive junction; (f) a second metal contact forming another terminal of said memory cell and extending through another one of said openings so as to contact said polysilicon layer on the other side of both said first and second semiconductive junctions and conductively coupled to said second region; (g) the surfaces of said third and fourth regions being free of any metal contact; (h) said first semiconductive junction serving as a programming diode when a voltage is applied across said first and second metal conductors with polarity and magnitude to cause reverse-bias breakdown of said first semiconductive junction.

Claim 15

A semiconductive memory cell, comprising: (a) a semiconductive body; (b) a layer of insulating material on a surface of said body; (c) a layer of polysilicon on said insulating layer and including a first region of first type conductivity, a second region of first type conductivity spaced laterally from said first region, a third region of second type conductivity between said first and second regions and forming a first semiconductive junction with said first region, said third region differing in impurity concentration from said first region, and a fourth region of second type conductivity between said first and second regions and forming a second semiconductive junction with said second region, said fourth region at least adjoining said third region and differing in impurity concentration from said second region, said first semiconductive junction having a lower reverse-bias breakdown voltage than said second semiconductive junction; (d) a relatively thin layer of insulating material on said polysilicon layer provided with openings therein through which electrical contacts can be made to said polysilicon layer; (e) a first metal contact forming one terminal of said memory cell extending over the surface of said polysilicon layer at least a distance overlying said first semiconductive junction and extending through one of said openings so as to contact said first region on one side of said first semiconductive junction; (f) a second metal contact forming another terminal of said memory cell and extending through another one of said openings so as to contact said polysilicon layer on the other side of both said first and second semiconductive junctions and conductively coupled to said second region; (g) the surfaces of said third and fourth regions being free of any metal contact; (h) said first semiconductive junction serving as a programming diode when a voltage is applied across said first and second metal conductors with polarity and magnitude to cause reverse-bias breakdown of said first semiconductive junction.

Claim 16

The invention according to claim 13, wherein said first metal contact extends over said polysilicon layer a distance beyond said first semiconductive junction.

Claim 17

The invention according to claim 13, wherein said first metal contact is made of aluminum.

Claim 18

The invention according to claim 13, wherein said first region and said first metal contact are self-aligned through said one opening in the relatively thin insulating layer.

Claim 19

The invention according to claim 13 wherein said insulating layer in (b) is sufficiently thicker than said polysilicon layer as to thermally insulate said polysilicon layer from said semiconductive body.