Double junction read only memory and process of manufacture

Claim 1

A process of manufacturing an integrated circuit matrix for a READ ONLY MEMORY comprising the steps of a. forming a plurality of transistors into a single die, b. forming isolation channels in said die to define separate rows of transistors having a common collector and electrically isolated from transistors in other rows, c. forming an electrically insulating layer over the upper surface of said die with openings therethrough to base and emitter regions of said transistors, d. forming an electrical contact to each common collector as row contacts of said matrix, e. applying ohmic contacts to said base and emitter regions through the openings in said insulating layer and electrically connecting together one emitter region in each row to thus form a plurality of electrically conducting matrix columns, and f. forming a highly conductive buried collector region along each row with said region extending only into lateral proximity with the base regions of the row on the opposite side of the base contact from the emitter contact, whereby said matrix is electrically programmable by application of a voltage between selected rows and columns.