Electrically alterable integrated circuit read only memory unit and process of manufacturing

Claim 2

A process of manufacturing an integrated circuit READ ONLY MEMORY matrix comprising the steps of diffusing transistors inTo a die in rows with each row thereof having a common collector, attaching a separate electrical contact to each common collector, forming electrical contacts in separate columns extending transversely of said rows with each column contact engaging the emitter of a transistor in a separate row thereof, applying pulsed electrical power between selected collector contacts and column contacts with the proper polarity and sufficient current to cause progressive degradation of the base-emitter junction of the transistor connected between said contacts, and continuously monitoring the reverse current resistance of the base-emitter junction of the transistor while applying said pulsed electrical power and terminating the application of power when the resistance decreases to a predetermined value.

Claim 3

The process of claim 1 further defined by applying a monitor pulse to said transistor between each power pulse for accomplishing said monitoring of the resistance of the base-emitter junction of the transistor to reverse current flow.

Claim 4

The process of claim 1 further defined by limiting the pulse height and pulse width of said power pulses to incrementally degrade the base-emitter junction with each pulse application.

Claim 5

The process of claim 3 further defined by monitoring the reverse current resistance of the base-emitter junction by applying low current reverse bias monitoring pulses across said base-emitter junction and terminating application of said power pulses upon predetermined reverse junction voltage with said monitor pulses.

Claim 6

A process of manufacturing an integrated circuit READ ONLY MEMORY matrix comprising the steps of forming a plurality of transistors in a die in rows with each row thereof having a common collector, attaching a separate electrical contact to each common collector, forming electrical contacts in separate columns extending transversely of said rows with each column contact engaging the emitter of a transistor in a separate row thereof, applying pulsed electrical power between the collector and emitter of a selected transistor of said matrix with sufficient current to incrementally degrade the base-emitter junction thereof, monitoring the resistance between the collector and emitter contacts of the selected transistor during pulsed power application as a measure of base-emitter junction resistance, and terminating power application at predetermined monitored resistance of the base-emitter junction to prevent damage to the adjacent base-collector junction of the selected transistor.

Claim 7

A process of manufacturing an integrated circuit READ ONLY MEMORY matrix comprising the steps of forming a plurality of transistors in a die in rows with each row thereof having a common collector, attaching a separate electrical contact to each common collector, forming electrical contacts in separate columns extending transversely of said rows with each column contact engaging the emitter of a transistor in a separate row thereof, applying pulsed electrical power between the collector and emitter of a selected transistor of said matrix with sufficient current to incrementally degrade the base-emitter junction thereof, monitoring the resistance between the collector and emitter contacts of the selected transistor during pulsed power application as a measure of base-emitter junction resistance, and terminating power application at predetermined monitored resistance of the base-emitter junction to prevent damage to the adjacent base-collector junction of the selected transistor.

Claim 8

The process of claim 5 further characterized by monitoring the resistance of the base-emitter junction by applying low level monitoring pulses between application of power pulses, and terminating application of power pulses at a predetermined emitter to collector resistance of the selected transistor.